Scalable power field effect transistor with improved heavy body structure and method of manufacture

• US 7,754,567 B2
• Filed: 06/16/2009
• Issued: 07/13/2010
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Huang, Ming-Huang, Wang, Qi, Sharp, Joelle
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US12/485,290
• Publication Number:
  US 20090253237A1
• Time in Patent Office: 392 Days
• Field of Search: 438/268, 438/270, 257/E21.41, 257/E21.418, 257/E21.419, 257/E21.42
• US Class Current: 438/270
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method for forming a field effect transistor (FET) includes the following steps. A well region of a first conductivity type is formed in a semiconductor region of a second conductivity type. A gate electrode is formed adjacent to but insulated from the well region. A source region of the second conductivity type is formed in the well region. A heavy body recess is formed extending into and terminating within the well region adjacent the source region. The heavy body recess is at least partially filled with a heavy body material having a lower energy gap than the well region.

Claims

1. A method of forming a field effect transistor (FET), comprising:

forming a well region of a first conductivity type in a semiconductor region of a second conductivity type;

forming a gate electrode adjacent to but insulated from the well region;

forming a source region of the second conductivity type in the well region;

forming a heavy body recess extending into and terminating within the well region adjacent the source region; and

at least partially filling the heavy body recess with a heavy body material comprising germanium and having a lower energy gap than the well region.

2. The method of claim 1 wherein the heavy body material comprises silicon germanium.

3. The method of claim 1 wherein the heavy body material comprises boron doped silicon germanium.

4. The method of claim 3 wherein the boron concentration is greater than 5×

10¹⁸ cm<sup>−

3</sup>.

5. The method of claim 1 wherein the heavy body material comprises poly silicon germanium.

6. The method of claim 1 wherein the heavy body material comprises epitaxial silicon germanium.

7. The method of claim 1 wherein the heavy body material comprises Si_1-xGe_x where x>

0.1.

8. The method of claim 1 wherein the heavy body material comprises greater than or equal to about 10 percent germanium mole fraction.

9. The method of claim 1 wherein the step of at least partially filling comprises:

forming a layer of SiGe using chemical vapor deposition; and

etching the deposited layer of SiGe so that a top surface of the SiGe in the heavy body recess is substantially coplanar with a top surface of the source region.

10. The method of claim 9 wherein the step of forming a layer of SiGe comprises implanting boron in-situ during SiGe deposition.

11. The method of claim 9 further comprising:

forming a trench extending into the semiconductor region, wherein the gate electrode is formed inside the trench.

12. The method of claim 11 further comprising:

prior to forming the layer of SiGe, forming a dielectric dome extending over the gate electrode and overlapping the source region; and

forming an interconnect layer contacting the source region and the heavy body material, wherein the dielectric dome insulates the gate electrode from the interconnect layer.

13. The method of claim 11 further comprising:

prior to forming the layer of SiGe, forming a dielectric cap filling an upper portion of the trench over the gate electrode, the dielectric cap having a top surface substantially coplanar with a top surface of the source region; and

forming an interconnect layer contacting the source region and the heavy body material, wherein the dielectric cap insulates the gate electrode from the interconnect layer.

14. The method of claim 11 further comprising:

prior to forming the gate electrode, forming a thick bottom dielectric filling a bottom portion of the trench; and

forming a gate dielectric lining the trench sidewalls, the gate dielectric being thinner than the thick bottom dielectric.

15. The method of claim 11 further comprising:

prior to forming the gate electrode;

forming a shield dielectric lining lower sidewalls and bottom of the trench;

forming a shield electrode filling a lower portion of the trench beneath the gate electrode; and

forming a gate dielectric extending along upper trench sidewalls, the gate dielectric being thinner than the shield dielectric.

16. The method of claim 1 wherein the step of least partially filling comprises:

filling the heavy body recess with SiGe using selective deposition such that SiGe is formed over exposed silicon surfaces; and

etching the SiGe so that a top surface of the SiGe in the heavy body recess is substantially coplanar with a top surface of the source region.

17. The method of claim 16 further comprising:

forming a trench extending into the semiconductor region, wherein the gate electrode is formed inside the trench.

18. The method of claim 17 further comprising:

prior to forming the layer of SiGe, forming a dielectric dome extending over the gate electrode and overlapping the source region; and

forming an interconnect layer contacting the source region and the heavy body material, wherein the dielectric dome insulates the gate electrode from the interconnect layer.

19. The method of claim 17 further comprising:

prior to forming the layer of SiGe, forming a dielectric cap filling an upper portion of the trench over the gate electrode, the dielectric cap having a top surface substantially coplanar with a top surface of the source region; and

forming an interconnect layer contacting the source region and the heavy body material, wherein the dielectric cap insulates the gate electrode from the interconnect layer.

20. The method of claim 17 further comprising:

prior to forming the gate electrode, forming a thick bottom dielectric filling a bottom portion of the trench; and

forming a gate dielectric lining the trench sidewalls, the gate dielectric being thinner than the thick bottom dielectric.

21. The method of claim 17 further comprising:

prior to forming the gate electrode;

forming a shield dielectric lining lower sidewalls and bottom of the trench;

forming a shield electrode filling a lower portion of the trench beneath the gate electrode; and

forming a gate dielectric extending along upper trench sidewalls, the gate dielectric being thinner than the shield dielectric.

22. The method of claim 1 wherein the heavy body recess is substantially V-shaped, and the step of at least partially filling comprises:

forming a layer of SiGe using chemical vapor deposition; and

etching to recess the layer of SiGe into the heavy body recess such that the SiGe does not overlap with the source region.

23. The method of claim 1 wherein the heavy body recess is substantially V-shaped, and the step of at least partially filling comprises:

filling the heavy body recess with SiGe using selective deposition such that a concentration of germanium in the SiGe decreases in a direction from the walls of the V-shaped heavy body recess toward a center of the heavy body recess; and

etching the SiGe using selective etching such that the SiGe remaining in the heavy body recess has a rounded upper surface.

24. The method of claim 1 further comprising:

prior to forming the gate electrode, forming a gate dielectric laterally extending over the well region and overlapping the source region, wherein the gate electrode is formed to laterally extend over the gate dielectric.

25. A method of forming a field effect transistor (FET), comprising:

forming a well region of a first conductivity type is a semiconductor region of a second conductivity type;

forming a gate electrode adjacent to but insulated from the well region;

forming a source region of the second conductivity type in the well region;

forming a heavy body recess extending into and terminating within the well region adjacent the source region; and

forming a heavy body region extending in the well region along a bottom of the heavy body recess, wherein the heavy body region comprises germanium and has a lower energy gap than that of the well region.

26. The method of claim 25 further comprising forming an interconnect layer substantially filling the heavy body recess so as to electrically contact the heavy body region and the source region.

27. The method of claim 25 wherein the heavy body region comprises silicon germanium.

28. The method of claim 25 wherein the step of forming a heavy body region comprises co-implanting boron and germanium into the heavy body recess to thereby form a boron doped silicon germanium region in the well region.

29. The method of claim 25 wherein the heavy body region comprises Si_1-xGe_x where x>

0.1.

30. The method of claim 25 wherein the heavy body region comprises greater than or equal to about 10 percent germanium mole fraction.

31. The method of claim 25 further comprising:

forming a trench extending into the semiconductor region, wherein the gate electrode is formed inside the trench.

32. The method of claim 31 further comprising:

prior to forming the heavy body recess, forming a dielectric layer filling an upper portion of the trench over the gate electrode and extending over a mesa region adjacent the trench; and

subsequent to forming the heavy body recess, co-implanting boron and germanium into the heavy body recess to thereby form a boron doped silicon germanium region in the well region.

33. The method of claim 32 further comprising:

prior to forming the gate electrode, forming a thick bottom dielectric filling a bottom portion of the trench; and

forming a gate dielectric lining the trench sidewalls, the gate dielectric being thinner than the thick bottom dielectric.

34. The method of claim 32 further comprising:

prior to forming the gate electrode;

forming a shield dielectric lining lower sidewalls and bottom of the trench;

forming a shield electrode filling a lower portion of the trench beneath the gate electrode; and

forming a gate dielectric extending along upper trench sidewalls, the gate dielectric being thinner than the shield dielectric.

35. The method of claim 25 further comprising:

prior to forming the gate electrode, forming a gate dielectric laterally extending over the well region and overlapping the source region, wherein the gate electrode is formed to laterally extend over the gate dielectric.