Method for production of an integrated circuit bar arrangement, in particular comprising a capacitor assembly, as well as an integrated circuit arrangement

• US 7,755,196 B2
• Filed: 09/19/2007
• Issued: 07/13/2010
• Est. Priority Date: 01/15/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Holz, Jurgen, Barth, Hans-Joachim
• Primary Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US11/857,944
• Publication Number:
  US 20080006905A1
• Time in Patent Office: 1,028 Days
• Field of Search: 257/499, 257/E23.144
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.

Claims

1. An integrated circuit arrangement comprising:

a first electrode layer which contains at least one first electrode;

a second electrode layer which contains at least one second electrode,

a dielectric layer between the first electrode layer and the second electrode layer and having at least one aperture that passes through the dielectric layer to the at least one first electrode,

wherein the second electrode layer includes a first electrically conductive layer overlying and adjacent to the dielectric layer but not within the at least one aperture, and a second electrically conductive layer overlying the first electrically conductive layer and extending into the at least one aperture and contacting the first electrode,

wherein the second electrically conductive layer comprises a liner/barrier layer, and

wherein the second electrode comprises an electrically conductive material different from the first electrically conductive layer and the second electrically conductive layer.

2. The circuit arrangement as claimed in claim 1, wherein the first electrically conductive layer comprises a material different from the second conductive layer, and wherein the first electrically conductive layer has a thickness different from the second electrically conductive layer.

3. The circuit arrangement as claimed in claim 1, wherein the first electrically conductive layer comprises a material different from the second conductive layer.

4. The circuit arrangement as claimed in claim 1, wherein the first electrically conductive layer has a thickness different from the second electrically conductive layer.

5. The circuit arrangement as claimed in claim 1, wherein a thickness difference between the combined thickness of the first electrically conductive layer and the second electrically conductive layer with respect to a thickness of the first electrically conductive layer is at least 20 nm.

6. The circuit arrangement as claimed in claim 1, wherein the circuit arrangement is produced using a method comprising:

forming a dielectric layer on an electrode layer including at least one electrode, wherein the dielectric layer has a thickness of less than 150 nm and is in contact with the at least one electrode;

applying at least one hard mask layer to the dielectric layer, wherein the at least one hard mask layer is configured to define a contact or via;

applying a resist layer to the hard mask layer;

structuring the hard mask layer using the resist layer, wherein the dielectric layer is not completely structured, and wherein a contact hole or a via is not completely opened;

removing residues of the resist layer;

after removing the residues of the resist layer, completing the structuring of the dielectric layer using the hard mask layer, and completely opening the contact hole or the via and exposing the at least one electrode in the electrode layer; and

removing the hard mask layer, wherein the hard mask layer comprises an electrically insulating layer.

7. The circuit arrangement as claimed in claim 1, wherein the circuit arrangement comprises a capacitor arrangement.