Stacked die module including multiple adhesives that cure at different temperatures

• US 7,755,204 B2
• Filed: 09/25/2003
• Issued: 07/13/2010
• Est. Priority Date: 05/08/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jackson, Timothy L., Cobbley, Chad A.
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Mitchell; James M
• Application Number:
  US10/672,750
• Publication Number:
  US 20040056342A1
• Time in Patent Office: 2,483 Days
• Field of Search: 257/783, 257/686, 257/777, 257/778, 257/782, 438/106, 438/123
• US Class Current: 257/782
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 156/10 : Methods of surface bonding and/or assembly therefor

Abstract

A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Claims

1. An integrated circuit comprising:

a stack comprising at least two semiconductor die, each of the semiconductor die being coupled together by a first adhesive, the first adhesive being curable at a first temperature; and

a substrate coupled to one of the at least two semiconductor die by a second adhesive, the second adhesive being curable at a second temperature lower than the first temperature.

2. The integrated circuit, as set forth in claim 1, wherein the topside surface area of one of the at least two semiconductor die is less than the topside surface area of a second of the at least two semiconductor die.

4. The integrated circuit, as set forth in claim 1, wherein at least one of the at least two semiconductor die comprises a memory die.

3. An integrated circuit comprising:

a stack comprising at least two semiconductor die, each of the semiconductor die being coupled together by a first adhesive, the first adhesive being curable at a first temperature; and

a substrate coupled to one of the at least two semiconductor die by a second adhesive, the second adhesive being curable at a second temperature lower than the first temperature;

wherein the stack of at least two semiconductor die is configured such that the stack comprises a shingle stack.

5. An integrated circuit comprising:

a stack comprising at least two semiconductor die, each of the semiconductor die being coupled together by a first adhesive, the first adhesive being curable at a first temperature; and

a substrate coupled to one of the at least two semiconductor die by a second adhesive, the second adhesive being curable at a second temperature lower than the first temperature;

wherein each die in the stack of at least two die is successively thinner than the previous die as the die approach the substrate.

6. An integrated circuit comprising:

a stack of at least two semiconductor die, each of the die being coupled to an adjacent die in the stack by a respective layer of a first adhesive prior to the stack being coupled to a packaging substrate, wherein the first adhesive is curable at a first temperature; and

a second adhesive disposed on an outer side of the stack to facilitate coupling the stack with the packaging substrate, wherein the second adhesive is curable at a second temperature lower than the first temperature.

7. The integrated circuit, as set forth in claim 6, wherein the topside surface area of one of the at least two semiconductor die is less than the topside surface area of a second of the at least two semiconductor die.

8. The integrated circuit, as set forth in claim 6, wherein at least one of the at least two semiconductor die comprises a memory die.

9. An integrated circuit package comprising:

a substrate; and

a die stack coupled to the substrate, wherein the die stack comprises at least two semiconductor die coupled together via a first adhesive that is curable at a first temperature and has been cured; and

a second adhesive disposed between the die stack and the substrate that is curable at a second temperature lower than the first temperature.

10. The integrated circuit package, as set forth in claim 9, wherein at least one of the at least two semiconductor die comprises a memory die.