Apparatus, system, and method for Z-culling

• US 7,755,624 B1
• Filed: 11/07/2008
• Issued: 07/13/2010
• Est. Priority Date: 12/19/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Hakura, Ziyad S., Langendorf, Brian K., Simeral, Brad W., Cox, Michael Brian
• Primary Examiner(s): Chauhan; Ulka
• Assistant Examiner(s): Prendergast; Roberta
• Application Number:
  US12/266,820
• Time in Patent Office: 613 Days
• Field of Search: 345/419, 345/421, 345/422, 345/426, 345/428, 345/503, 345/506, 345/519, 345/539, 345/548
• US Class Current: 345/421
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/405 using Z-buffer

Abstract

A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.

Claims

1. An integrated circuit for culling tiles in a graphics processing system, comprising:

a first processor including;

a vertex engine to perform vertex processing;

a coarse-raster module configured to receive data from the vertex engine and rasterize primitives at a coarse level of resolution corresponding to tiles having groups of pixels and generate information sufficient to determine a Znear for tiles corresponding to a nearest Z distance of a tile with respect to an eyepoint;

a coarse Z-cull module receiving an output of said raster module, the Z-cull module constructing a surface of nearest and farthest objects being rendered and determining Z depth data for near and far objects to generate information for determining tiles that may be culled by comparing Z depth information of incoming tiles with Znear and Zfar values of previously observed tiles having the same tile location, where Zfar is a farthest Z distance with respect to said eyepoint;

a fine raster module coupled to an output of said Z-cull module configured to generate Zfar values for incoming primitives at a fine resolution corresponding to screen regions at least as small as 1 pixel in size, each Zfar value corresponding to a conservative estimate of a farthest Z value with respect to an eyepoint; and

an on-chip cache memory configured to coalesce said Zfar values generated from said fine raster module, coalesce coverage masks across samples, generate Zfar values for samples within tiles, and provide a maximum Zfar value for covered tiles to said Z-cull module;

said first processor being operative to generate coarse Z cull information for determining tiles capable of being culled;

said first processor performing vertex processing, rasterization, and Z-culling on a frame-by-frame basis to process frames identical to those processed by a second processing unit but with said first processing unit working one frame ahead of said second processing unit and at a coarser level of resolution such that said second processing unit begins the processing of a new frame with an initial set of culling information generated by said first processor for the same frame;

wherein a coalescence cache includes a coalescing policy for performing for an incoming new tile at least one of dropping said new incoming tile, coalescing said new incoming tile with exiting tiles, or creating a new entry for said incoming tile; and

wherein said second processor performs a second step of vertex processing, a second step of rasterization, and a second step of Z-culling for the current frame at a time corresponding to one frame after said first processor processes the current frame.

2. The integrated circuit of claim 1, wherein the coalescence cache is configured to compare Zfar values of incoming tiles with cached Zfar values and perform updates of said coalescence cache to maintain a conservative estimate of Zfar values of samples.

3. The integrated circuit of claim 1, wherein the coalescence cache is configured to coalesce coverage masks for incoming and stored tiles.

4. The integrated circuit of claim 1, wherein said first processor and said second processor are disposed on a common chip.

5. The integrated circuit of claim 1, wherein said coarse Z cull module is configured to generate a threshold Z value for distinguishing occluders within a group of tiles.

6. The integrated circuit of claim 1, wherein said coarse Z cull module is configured to identify a new tile as an occluder in response to a Zfar of said new tile being closer to an eyepoint than a previous Znear value for an (x,y) location of said new tile.

7. The integrated circuit of claim 1, wherein said coarse Z cull module is configured to identify a new tile as an occluded tile in response to a Znear of said new tile being farther away from an eyepoint that a Zfar value in said cache for said (x,y) location of said new tile.

8. A system for culling tiles in a graphics processing system, comprising:

a first processor performing Z-culling at a coarse level of resolution;

a second processor performing Z-culling at a fine level of resolution;

the first processor and the second processor having a temporal offset such that the first processor is working one frame ahead of the second processor with the first processor providing the second processor with coarse Z-cull information such that the second processor begins the processing of a new frame with an initial set of coarse culling information generated by said first processor for the same frame;

wherein a coalescence cache includes a coalescing policy for performing for an incoming new tile at least one of dropping said new incoming tile, coalescing said new incoming tile with exiting tiles, or creating a new entry for said incoming tile; and

wherein said second processor performs a second step of vertex processing, a second step of rasterization, and a second step of Z-culling for the current frame at a time corresponding to one frame after said first processor processes the current frame.

9. The system of claim 8, wherein the first processor and the second processor are disposed on a single integrated circuit.

10. The system of claim 8, wherein the first processor and the second processor are disposed on separate integrated circuits.