Integrated circuit memory device having dynamic memory bank count and page size

• US 7,755,968 B2
• Filed: 08/07/2007
• Issued: 07/13/2010
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kim, Jun, Knorpp, Kurt T., Bellows, Chad A., Richardson, Wayne S., Ching, Michael, Woo, Steven
• Primary Examiner(s): Elms; Richard
• Assistant Examiner(s): Yang; Han
• Application Number:
  US11/834,915
• Publication Number:
  US 20070268765A1
• Time in Patent Office: 1,071 Days
• Field of Search: 365/220, 365/196, 365/205, 365/222, 365/230.03, 365/185.11, 365/185.12
• US Class Current: 365/230.03
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.

Claims

1. An integrated circuit memory device, comprising:

a storage array having an adjustable number of accessible memory banks;

a row of sense amplifiers to access storage cells in the storage array; and

memory access control circuitry providing a first number of accessible memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and providing a second number of accessible memory banks and a second page size in the integrated circuit memory device in a second mode of operation, the memory access control circuitry including logic circuitry to adjust the number of accessible memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device, wherein the second number is different from the first number, and the first page size and second page size correspond to distinct numbers of accessible storage cells in the storage array that are accessible as a respective page.

2. The integrated circuit memory device of claim 1, including circuitry to transfer data from one or more rows of storage cells in the storage array to the row of sense amplifiers in the integrated circuit memory device in accordance with a mode of operation of the integrated circuit memory device, wherein the mode of operation is selected from the set consisting of the first mode and the second mode.

3. The integrated circuit memory device of claim 2, wherein the memory access control circuitry is configured to transfer, while performing a memory access operation in the second mode of operation, first data from a first row of storage cells in the storage array to a first plurality of the sense amplifiers, and to transfer second data from a second row of storage cells to a second plurality of the sense amplifiers.

12. The integrated circuit memory device of claim 1, wherein the memory access control circuitry adjusts the number of accessible memory banks in the integrated circuit memory device and the page size of the integrated circuit memory device in response to a mode control signal.

13. The integrated circuit memory device of claim 12, wherein the mode control signal is provided from an initialization register.

14. The integrated circuit memory device of claim 12, wherein the mode control signal is generated by a master device.

15. The integrated circuit memory device of claim 14, wherein the master device generates the mode control signal from a power consumption value.

4. A method for operation of an integrated circuit memory device, comprising:

transitioning between a first mode of operation, providing a first number of accessible memory banks and a first page size in the integrated circuit memory device, and a second mode of operation, providing a second number of accessible memory banks and a second page size in the integrated circuit memory device, including;

adjusting the number of accessible memory banks in the integrated circuit memory device; and

adjusting the page size of the integrated circuit memory device;

wherein the second number is different from the first number, and the first page size and second page size correspond to distinct numbers of accessible storage cells in the storage array that are accessible as a respective page.

5. The method of claim 4, further comprising:

while performing a memory access operation, transferring data from one or more rows of storage cells to a row of sense amplifiers in the integrated circuit memory device in accordance with a mode of operation of the integrated circuit memory device, wherein the mode of operation is selected from the set consisting of the first mode and the second mode.

6. The method of claim 5, including, in the second mode of operation, while performing the memory access operation, transferring first data from a first row of storage cells to a first plurality of the sense amplifiers, and transferring second data from a second row of storage cells to a second plurality of the sense amplifiers.

16. The method of claim 4, wherein the transitioning between the first mode of operation and the second mode of operation is performed in response to a mode control signal.

17. The method of claim 16, wherein the mode control signal is provided from an initialization register.

18. The method of claim 16, wherein the mode control signal is generated by a master device.

19. The method of claim 18, wherein the master device generates the mode control signal from a power consumption value.

7. An integrated circuit memory device, comprising:

an adjustable number of accessible memory banks;

means for transferring data to a plurality of sense amplifiers; and

means for transitioning between a first mode of operation, providing a first number of accessible memory banks and a first page size in the integrated circuit memory device, and a second mode of operation, providing a second number of accessible memory banks and a second page size in the integrated circuit memory device, including means for adjusting the number of accessible memory banks in the integrated circuit memory device, and means for adjusting the page size of the integrated circuit memory device, wherein the second number is different from the first number, and the first page size and second page size correspond to distinct numbers of accessible storage cells in the storage array that are accessible as a respective page.

8. The integrated circuit memory device of claim 7, wherein the means for transitioning operates in response to a mode control signal.

9. The integrated circuit memory device of claim 8, wherein the mode control signal is provided from an initialization register.

10. The integrated circuit memory device of claim 8, wherein the mode control signal is generated by a master device.

11. The integrated circuit memory device of claim 10, wherein the master device generates the mode control signal from a power consumption value.