Digital clock generating circuit and method of operation

• US 7,756,231 B2
• Filed: 01/09/2007
• Issued: 07/13/2010
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Quiroga, Emilio J.
• Primary Examiner(s): Payne; David C
• Assistant Examiner(s): Stevens; Brian J
• Application Number:
  US11/621,420
• Publication Number:
  US 20080165753A1
• Time in Patent Office: 1,281 Days
• Field of Search: 370/342, 327/291, 375/354
• US Class Current: 375/354
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

A digital clock generation circuit (200) and method of operation (400). A digital clock (250) produces an output (220) with a first frequency or a second frequency. A clock control circuit (204, 206) selectively sets the digital clock (250) to produce either the first frequency or the second frequency. An excess pulse counter (212) determines a number of pulses produced by the digital clock (250) at the second frequency that differs in the number of pulses that would have been produced at the first frequency, had the clock frequency change to the second frequency not occurred. An output phase correction circuit (230, 232, 212) removes, in response to the digital clock (250) changing from producing the second frequency to producing the first frequency, the number of pulses from the output (220) that were counted by the excess pulse counter (212).

Claims

1. A digital clock generation circuit, comprising:

a digital clock configurable to produce an output at either one of a first frequency and a second frequency, the second frequency being different from the first frequency;

a clock control circuit controlling the digital clock and selectively setting the digital clock to produce the output at one of the first frequency and the second frequency;

an excess pulse counter, communicatively coupled to the clock control circuit and the digital clock, the excess pulse counter determining a number of pulses produced by the digital clock at the second frequency that differs from the number of pulses that would have been produced by the digital clock at the first frequency;

an output phase correction circuit, communicatively coupled to the digital clock, the excess pulse counter, and the clock control circuit, the output phase correction circuit removing, in response to the clock control circuit commanding the digital clock to change from producing an output at the second frequency to producing an output at the first frequency, the number of pulses from the output that were counted by the excess pulse counter; and

a fixed frequency clock producing a fixed frequency output at a third frequency,

wherein the digital clock accepts a reference base clock input at a reference frequency,

wherein the digital clock produces the output at the first frequency by dividing the reference frequency by a first integer and produces the output at the second frequency by dividing the reference frequency by a second integer, and

wherein the fixed frequency clock produces the fixed frequency output by dividing, when the output is produced at the first frequency, a frequency of the output by a first factor and by dividing, when the output is produced at the second frequency, the frequency of the output by a second factor, the value of the first integer multiplied by the first factor being equivalent to the second integer multiplied by the second factor.

2. The digital clock generation circuit of claim 1, wherein the output phase correction circuit disables the output for the number of pulses.

3. The digital clock generation circuit of claim 1, further comprising:

at least one of a receiver and a transmitter;

a digital signal processing circuit comprising at least one circuit operating at a first frequency and at least one circuit operating at a second frequency; and

a clock output stage, communicatively coupled to the output phase correction circuit and the digital signal processing circuit, adapted to providing, to the digital signal processing circuit, the output with the number of pulses removed.

4. The digital clock generation circuit of claim 1, wherein the excess pulse counter counts up to one less than the first integer and resets in response to exceeding a count of one less than the first integer.

5. The digital clock generation circuit of claim 1, wherein the excess pulse counter operates by:

updating a counter by an integer value in response to;

a pulse produced by the fixed frequency output, and

setting the digital clock to produce the output at the second frequency, and

decrementing the counter in response to setting the output to the first frequency and determining that the counter has a non-zero count.

6. The digital clock generation circuit of claim 5, wherein the output phase correction circuit removes one pulse from the output in response to decrementing the counter.

7. The digital clock generation circuit of claim 1, further comprising a constant timing reference, communicatively coupled to the clock control circuit, wherein the constant timing reference is adapted to produce a timing signal with a non-interrupted timing interval that is independent of a frequency of the output generated by the digital clock.

8. The digital clock generation circuit of claim 7, further comprising a shifted clock counter, communicatively coupled to the constant timing reference, wherein the fixed frequency output produces an integer number of pulses to be accumulated by the shifted clock counter, whereby the integer number of pulses represents a number of pulses produced by the digital clock, within the timing interval produced by the constant timing reference, at the second frequency that differ from the number of pulses that would have been produced by the digital clock at the first frequency.

9. A method, with a digital clock generating circuit, for generating a reference clock signal, the method comprising:

producing an output that is configurable to be at either one of a first frequency and a second frequency, the second frequency being different from the first frequency;

setting the output to operate at the second frequency,

determining a number of pulses produced in the output at the second frequency that differs from a number of pulses that would have been produced in the output at the first frequency, within a time period specified by a constant timing reference, and accumulating said number of pulses;

removing, in response to setting the output to change from the second frequency to the first frequency, the number of pulses accumulated; and

producing a fixed frequency output at a third frequency,

wherein producing the output at the first frequency comprises dividing the reference frequency by a first integer and producing the output at the second frequency comprises dividing the reference frequency by a second integer, and wherein producing the fixed frequency output comprises dividing, when the output is produced at the first frequency, a frequency of the output by a first factor and dividing, when the output is produced at the second frequency, the frequency of the output by a second factor, the value of the first integer multiplied by the first factor being equal to the second integer multiplied by the second factor.

10. The method of claim 9, wherein the removing comprises disabling the output for the number of pulses.

11. The method of claim 9, wherein the fixed frequency output produces one pulse for each expiration of a fixed timing reference, the fixed timing reference producing one pulse for each pulse produced in the output at the second frequency that differs from the number of pulses that would have been produced in the output at the first frequency.

12. The method of claim 11, wherein the determining he number of pulses comprises:

incrementing a counter in response a pulse produced by the fixed frequency

output and setting the output to the second frequency, and decrementing the counter in response to the setting the output to the first

frequency and determining that the counter has a non-zero count.

13. The method of claim 12, wherein the removing comprises removing one pulse from the output in response to decrementing the counter.

14. A digital clock generation circuit, comprising:

a digital clock configurable to produce an output at either one of a first frequency and a second frequency, the second frequency being different from the first frequency;

a clock control circuit controlling the digital clock and selectively setting the digital clock to produce the output at one of the first frequency and the second frequency;

a constant timing reference producing a non-interrupted timing interval that is independent of a frequency being generated by the digital clock generation circuit, the timing interval comprising an integer number of pulses produced by the digital clock at the second frequency that differs from a number of pulses that would have been produced by the digital clock at the first frequency during the timing interval;

an excess pulse counter, communicatively coupled to the clock control circuit, the constant timing reference, and the digital clock, the excess pulse counter determining a number of pulses produced by the digital clock at the second frequency that differs from the number of pulses that would have been produced by the digital clock at the first frequency during the timing interval; and

an output phase correction circuit, communicatively coupled to the digital clock, the excess pulse counter, and the clock control circuit, the output phase correction circuit removing, in response to the clock control circuit commanding the digital clock to change from producing an output at the second frequency to producing an output at the first frequency, the number of pulses from the output that were counted by the excess pulse counter.

15. The digital clock generation circuit of claim 14, further comprising a digital signal processing circuit including at least one circuit operating at a first frequency and at least one circuit operating at a second frequency, wherein the at least one circuit operating at the first frequency processes wideband code division multiple access (WCDMA) signals and the at least one circuit operating at the second frequency processes general system for mobile (GSM) signals.

16. The digital clock generation circuit of claim 15, wherein operation of the at least one circuit at the first frequency is temporarily interrupted in order to operate the at least one circuit at the second frequency to temporarily process GSM signals.