Integrated circuit device and signal transmission system

• US 7,757,022 B2
• Filed: 08/04/2004
• Issued: 07/13/2010
• Est. Priority Date: 08/04/2004
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kato, Naoki, Sasaki, Yasuhiko
• Primary Examiner(s): Kindred; Alford W
• Assistant Examiner(s): Abad; Farley J
• Application Number:
  US11/630,387
• Publication Number:
  US 20080052430A1
• Time in Patent Office: 2,169 Days
• Field of Search: 710/71
• US Class Current: 710/71
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

Some interface signals are selected from among signals of a plurality of different parallel interfaces, then being multiplexed onto a serial connection. A transmitter of a signal transmission system includes an interface-signal selector IFS, and a transfer programmer TP for issuing a control signal to instruct the selection from among the parallel interfaces. The transfer programmer TP implements the multiplexing of the selected interface signals in such a manner that the specification of the parallel interfaces is satisfied. Also, the transfer programmer TP changes, as occasion requires, the control signal to instruct which interfaces to select. This change allows the interface signals to be multiplexed onto the serial connection while dynamically changing the interface signals to be multiplexed.

Claims

1. An integrated circuit device for multiplexing parallel data of a plurality of parallel interfaces into serial data, said integrated circuit device, comprising:

a storage device,

a signal send-out circuit which outputs data on a one-bit basis to a transmission path connected to said integrated circuit device, said data being stored in said storage device,

an interface-signal selector which outputs parallel data of selected parallel interfaces to said storage device, said interface-signal selector being so configured as to be able to input said parallel data of said plurality of parallel interfaces, and

a transfer programmer which issues a control signal to said interface-signal selector, said control signal notifying said interface-signal selector of said parallel interfaces which are to be selected thereby,

wherein said storage device has a plurality of slots each storing the data output from the interface-signal selector for a respective parallel interface of the plurality of parallel interfaces as serial data,

wherein said storage device has a header information part which stores header information indicating which one of said plurality of parallel interfaces uses which one of the plurality of slots and in order in which the interface-signal selector selects the parallel interfaces, and

wherein said signal send-out circuit outputs said header information in addition to said serial data stored in said plurality of slots on a one bit basis to said transmission path.

2. The integrated circuit device according to claim 1, wherein said plurality of parallel interfaces differ from each other in at least one of transmission frequency, bit width of said data signal, configuration of said control signal, and transmission/reception protocol.

3. The integrated circuit device according to claim 1, wherein said transfer programmer

detects a change in a single or a plurality of predetermined bit data included in said parallel data of said plurality of parallel interfaces, and

determines parallel interfaces in which said change has occurred as said parallel interfaces which are to be selected by said interface-signal selector.

4. The integrated circuit device according to claim 1, wherein said transfer programmer

receives an external selection signal from an external device, said external selection signal instructing necessity or unnecessity for said selection of each of said plurality of parallel interfaces, and, in accordance with said external selection signal,

determines said parallel interfaces which are to be selected.

5. The integrated circuit device according to claim 1, wherein said transfer programmer

holds first information about transmission frequency and bit width of each of said plurality of parallel interfaces, and

generates said selection signal based on said first information.

6. The integrated circuit device according to claim 5, wherein said transfer programmer

further holds second information about priorities among said plurality of parallel interfaces, and

generates said selection signal based on said first information and said second information.

7. An integrated circuit device for reconstructing parallel data of a plurality of parallel interfaces from multiplexed serial data, said integrated circuit device, comprising:

a first storage device which has a plurality of slots that each stores data received from a transmission path connected to said integrated circuit device for a respective parallel interface of the plurality of parallel interfaces as serial data, the first storage device having a header information part which stores header information indicating which one of said plurality of parallel interfaces uses which one of the plurality of slots as serial data,

a second storage device which stores said serial data in such a manner that said serial data is separated into said parallel data for each of said parallel interfaces, said serial data being stored into said first storage device, and

a reception programmer which controls said data transmission from said first storage device to said second storage device based on a predetermined multiplexing rule,

wherein said predetermined multiplexing rule is notified from another integrated circuit device from which said serial data is transmitted as said header information included in said transmitted serial data and indicates an order in which said parallel data for said plurality of parallel interfaces had been multiplexed.