Semiconductor integrated circuit apparatus

• US 7,757,062 B2
• Filed: 03/12/2007
• Issued: 07/13/2010
• Est. Priority Date: 03/13/2006
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Shimura, Hidekichi
• Primary Examiner(s): Kim; Matt
• Assistant Examiner(s): Ahmed; Hamdy S
• Application Number:
  US11/684,897
• Publication Number:
  US 20070214336A1
• Time in Patent Office: 1,219 Days
• Field of Search: 711/167
• US Class Current: 711/167
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/225 Clock input buffers

Abstract

A semiconductor integrated circuit apparatus that enables function blocks in a semiconductor integrated circuit freely to vary power supply voltage and system clock frequency on the time axis, and also to exchange data among themselves. In a semiconductor integrated circuit apparatus 100, a first function block 110 has a first clock generation circuit 111 that generates a first system clock supplied to circuitry in a function block, first internal memory 112 in which data is read/written by means of the first system clock, and a selector 113 that selects the first system clock or a second system clock and supplies the selected clock to first internal memory 112. A clock selected by selector 113 from the first system clock or the second system clock is supplied as the clock supplied to first internal memory 112.

Claims

1. A semiconductor integrated circuit apparatus, comprising:

a first functioner that includes;

a first clock generator formed with a phase-locked loop that generates a first system clock;

a first internal memory in which data is at least one of written to and read from, using said first system clock; and

a first selector; and

a second functioner that includes;

a second clock generator formed with a phase-locked loop that generates a second system clock;

a second internal memory in which data is at least one of written to and read from using said second system clock; and

a second selector, wherein;

said first internal memory stores a value representing an operating voltage and a value representing an operating frequency corresponding to work of said second functioner, and a division ratio of an output signal of said first clock generator, in a form of an operation program,

said second internal memory stores a value representing an operating voltage and a value representing an operating frequency corresponding to work of said first functioner, and a division ratio of an output signal of said second clock generator, in a form of an operation program,

said first functioner reads and executes said operation program from said first internal memory, said second selector selects said first system clock from among said first system clock and said second system clock as a clock to operate said second internal memory, said first functioner and said second internal memory being operated and synchronized using said first system clock, when data in said first functioner is at least one of read from and written to said second internal memory,

said second functioner reads and executes said operation program from said second internal memory, said first selector selects said second system clock from among said first system clock and said second system clock as a clock to operate said first internal memory, said second functioner and said first internal memory being operated and synchronized using said second system clock, when data in said second functioner is at least one of read from and written to said first internal memory.

2. The semiconductor integrated circuit apparatus of claim 1, wherein:

a frequency of said first system clock is determined in accordance with a computational processing amount of said first functioner; and

a frequency of said second system clock is determined in accordance with a computational processing amount of said second functioner.

3. The semiconductor integrated circuit apparatus of claim 1, wherein a frequency of said first system clock and a frequency of said second system clock have no correlation.

4. The semiconductor integrated circuit apparatus of claim 1, wherein:

said first clock generator generates said first system clock necessary to process a computational processing amount that varies depending on a time axis of said first functioner, based on a supplied system clock external to said semiconductor integrated circuit; and

said second clock generator generates said second system clock necessary to process a computational processing amount that varies depending on a time axis of said second functioner, based on the supplied system clock external to said semiconductor integrated circuit.

5. The semiconductor integrated circuit apparatus of claim 1, wherein:

said first functioner comprises a general-purpose CPU; and

said second functioner comprises a multifunction DSP.

6. The semiconductor integrated circuit apparatus of claim 1, wherein:

said second functioner comprises a plurality of functioners, said plurality of functioners, comprising;

a clock generator that generates a system clock supplied to one of said plurality of functioners; and

an internal memory in which data is at least one of read from and written to using said system clock.

7. The semiconductor integrated circuit apparatus of claim 1, wherein said first internal memory and said second internal memory comprise one of a register file and a cache memory.

8. The semiconductor integrated circuit apparatus of claim 1, further comprising a plurality of functioners that correspond to said second functioner.

9. The semiconductor integrated circuit apparatus of claim 1, wherein a DMA controller controls mutual at least one of reading and writing between memories in functioners corresponding to a plurality of second functioners.