Multi-bit memory device and memory system

• US 7,757,153 B2
• Filed: 11/30/2006
• Issued: 07/13/2010
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong-Soo, Hwang, Sang-Won
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US11/605,977
• Publication Number:
  US 20070234183A1
• Time in Patent Office: 1,321 Days
• Field of Search: 714/763, 714/710
• US Class Current: 714/763
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A nonvolatile memory device, memory system and read method are disclosed. The memory device comprises a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1, a page buffer configured to perform a read operation adapted to read data from the memory cell array and output read data, an error correction circuit configured to detect and correct an error in read data stored in a memory block K and generate corresponding error information, and a control circuit configured to reduce the number of bits stored in the plurality of memory cells for memory block K from N to J, where J is an integer less than N but greater than zero, in response to the error information.

Claims

1. A nonvolatile memory device comprising:

a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1;

a page buffer configured to perform a read operation adapted to read data from the memory cell array and output read data;

an error correction circuit configured to detect and correct an error in read data stored in a memory block K and generate corresponding error information; and

a control circuit configured to reduce the number of bits stored in the plurality of memory cells for memory block K from N to J, where J is an integer less than N but greater than zero, in response to the error information.

2. The nonvolatile memory device of claim 1, wherein the memory cell array comprises a main data storage region adapted to store data and a spare data storage region adapted to store spare data associated with the data stored in the main storage region.

3. The nonvolatile memory device of claim 2, wherein the spare data comprises bit number data defining respectively the number of bits stored in the memory cells of each one of the plurality of memory blocks.

4. The nonvolatile memory device of claim 3, wherein the bit number data comprises a single-bit or multi-bit flag.

5. The nonvolatile memory device of claim 2, wherein the spare data storage region includes independent spare data associated with each one of the plurality of memory blocks.

6. The nonvolatile memory device of claim 1, wherein the control circuit is further configured to define memory block K as a bad block.

7. The nonvolatile memory device of claim 1, wherein the control circuit is further configured to perform a copyback operation for data stored in memory block K into a new memory block.

8. The nonvolatile memory device of claim 1, wherein the control circuit is further configured to control the page buffer to perform the read operation.

9. The nonvolatile memory device of claim 1, wherein the memory cell array comprises a NAND flash memory cell array.

10. The nonvolatile memory device of claim 8, wherein the N is equal to 2.

11. A non-volatile memory system comprising:

a memory controller configured to control read operations associated with a nonvolatile memory device, the nonvolatile memory device comprising;

a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1, wherein the memory cell array comprises a main data storage region adapted to store data and a spare data storage region adapted to store spare data associated with the data stored in the main storage region; and

a page buffer configured to perform the read operation in relation to the memory cell array and output read data;

the memory controller being configured to implement an error correction capability (ECC) adapted to detect and correct an error in the read data stored in a memory block K, and reduce the number of bits stored in the plurality of memory cells for memory block K from N to J, where J is an integer less than N but greater than zero, in response to the error detection.

12. The nonvolatile memory system of claim 11, wherein the spare data comprises a single-bit or multi-bit flag indicating that any one of the plurality of memory blocks is a bad block.

13. The nonvolatile memory system of claim 11, wherein the memory controller comprises a separate error correction circuit implementing the ECC.

14. The nonvolatile memory system of claim 11, wherein nonvolatile memory device comprises a control circuit configured to implement the ECC under the control of the memory controller.

15. The nonvolatile memory system of claim 14, wherein the control circuit comprises an address decoding and control circuit.

16. The nonvolatile memory system of claim 14, wherein the memory controller is further configured to execute software adapted to detect and correct the error and generate corresponding error information;

and

wherein the control circuit is adapted to modify spare data in the spare data storage region to reduce the number of bits stored in the plurality of memory cells for memory block K from N to J in response to the error information.

17. A read method for a nonvolatile memory device comprising a plurality of memory blocks, each comprising memory cells adapted to store N bits, where N is an integer greater than 1, the method comprising:

upon receiving an externally applied read command associated with a memory block K, determining whether read data stored in memory block K is single-bit data or multiple-bit data;

if the read data is single-bit data and contains an error,

reading and performing an error correction operation on the single-bit data, and marking memory block K as a bad block;

else if, the read data is multi-bit data and contains an error,

reading and performing an error correction operation on the multi-bit data, and reducing the number of bits stored in the memory cells of memory block K from N to J, where J is an integer less than N but greater than zero.

18. The read method of claim 17, wherein the determination of whether the read data stored in memory block K is single-bit data or multiple-bit data controls the manner by which a page buffer performs the read operation.

19. The read method of claim 17, wherein in conjunction with marking memory block K as a bad block, a copyback operation is performed with respect to the read data stored in memory block K to a new memory block.

20. The read method of claim 17, wherein multi-bit data is 2 bit data and is read as a least significant bit or a most significant bit.