Method and system to construct a data-flow analyzer for a bytecode verifier
First Claim
1. A processor, comprising:
- a fetch logic configured to retrieve a plurality of instructions from a memory, wherein the plurality of instructions are from a first native instruction set of the processor; and
a decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions;
wherein the processor is configurable to execute the plurality of instructions and to verify that types of values exchanged between the plurality of instructions are correct,wherein when the processor is configured to verify types of values, each instruction in the first native instruction set is associated with a micro-sequence configured to perform type verification corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the types of the values exchanged between the plurality of instructions are verified, andwhen the processor is configured to execute the plurality of instructions, each instruction in a subset of the first native instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when the micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction,wherein a micro-sequence is one or more instructions from a second native instruction set of the processor.
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Abstract
The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
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Citations
22 Claims
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1. A processor, comprising:
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a fetch logic configured to retrieve a plurality of instructions from a memory, wherein the plurality of instructions are from a first native instruction set of the processor; and a decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions; wherein the processor is configurable to execute the plurality of instructions and to verify that types of values exchanged between the plurality of instructions are correct, wherein when the processor is configured to verify types of values, each instruction in the first native instruction set is associated with a micro-sequence configured to perform type verification corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the types of the values exchanged between the plurality of instructions are verified, and when the processor is configured to execute the plurality of instructions, each instruction in a subset of the first native instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when the micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction, wherein a micro-sequence is one or more instructions from a second native instruction set of the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for verifying that types of values exchanged between a plurality of instructions from a first native instruction set of a processor are correct, comprising:
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configuring the processor to verify types of values instead of executing instructions in the first native instruction set, wherein configuring comprises associating each instruction in the first native instruction set with a micro-sequence configured to perform type verification corresponding to the instruction; responsive to fetching and decoding each instruction in the plurality of instructions, executing the micro-sequence associated with the instruction, wherein the types of the values exchanged between the plurality of instructions are verified; and reconfiguring the processor to execute instructions in the first native instruction set after the types of the values are verified, wherein reconfiguring comprises associating each instruction in a subset of the first native instruction set with a micro-sequence configured to perform a function of the instruction, wherein all other instructions in the first native instruction set are executed directly by the processor, wherein a micro-sequence is one or more instructions from a second native instruction set of the processor. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A system, comprising:
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a first processor; and a second processor coupled to the first processor, the second processor comprising; a fetch logic configured to retrieve a plurality of instructions from a memory, wherein the plurality of instructions are from a first native instruction set of the second processor; and a decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions; wherein the second processor is configurable to execute the plurality of instructions and to verify that types of values exchanged between the plurality of instructions are correct, wherein when the second processor is configured to verify types of values, each instruction in the first native instruction set is associated with a micro-sequence configured to perform type verification corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the types of the values exchanged between the plurality of instructions are verified, and when the second processor is configured to execute the plurality of instructions, each instruction in a subset of the first native instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when the micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction, wherein a micro-sequence is one or more instructions from a second native instruction set of the second processor. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification