Anti-stiction coating

• US 7,758,912 B2
• Filed: 11/07/2007
• Issued: 07/20/2010
• Est. Priority Date: 11/26/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Reboa, Paul F.
• Primary Examiner(s): Talbot, Brian K
• Application Number:
  US11/936,710
• Publication Number:
  US 20080063790A1
• Time in Patent Office: 986 Days
• Field of Search: 427/58, 427/255.27, 427/289
• US Class Current: 427/58
• CPC Class Codes: B81B 3/0005 Anti-stiction coatings
• CPC Class Codes: B81B 3/0013 Structures dimensioned for mechanical prevention of stiction, e.g. spring with increased stiffness

Abstract

One embodiment of a microelectronic device includes a movable plate including a lower surface, a bump positioned on the lower surface, and an anti-stiction coating positioned only on the bump.

Claims

1. A process of manufacturing microelectronic devices, comprising:

placing a wafer in a deposition chamber, said wafer comprising a number of microelectronic devices, said microelectronic devices comprising a number of bump regions, said bump regions comprising a dielectric material; and

depositing an anti-stiction coating only on said bump regions,

in which said anti-stiction coating is configured to react with said dielectric material of said bump regions.

2. The process of claim 1 in which said process further comprises separating and individually packaging said microelectronic devices.

3. The process of claim 1 wherein said depositing comprises vapor depositing a fluorinated long-chain silane only on said bump regions.

4. The process of claim 1 wherein said deposition chamber is an enclosed deposition chamber.

5. The process of claim 1 wherein said anti-stiction coating is manufactured from a precursor chosen from one of fluorinated octyltrichlorosilane (FOTS), fluorinated decyltrichlorosilane (FDTS), dichlorodimethylsilane (DDMS), octyltrichlorosilane (OTS) and octadecyltrichlorosilane (ODTS).

6. The process of claim 1, prior to said depositing an anti-stiction coating, further comprising depositing a carboxylic acid on said wafer.

7. The process of claim 6 wherein said carboxylic acid is chosen from one of benzoic acid, perfluorobenzoic acid, lauric acid, and perfluorooctanoic acid.

8. The process of claim 6 wherein said carboxylic acid deposits only non-bump regions of said wafer.

9. A process of depositing an anti-stiction coating, comprising:

enclosing a microelectromechanical device (MEMS device) in a deposition chamber, said MEMS device including a bump area, said bump area comprising a dielectric material; and

depositing an anti-stiction coating only on said bump area,

in which said anti-stiction coating is configured to react with said dielectric material of said bump area.

10. The process of claim 9 wherein said coating comprises a hydrocarbon chain.

11. The process of claim 9 wherein said bump area is coated with SiO₂ and wherein said anti-stiction coating coats said SiO₂.

12. The process of claim 9 wherein said MEMS device comprises a plurality of movable pixel plates, each of said pixel plates including at least one bump area on a lower side thereof.

13. The process of claim 9 wherein said depositing comprises vapor deposition.

14. The process of claim 9 wherein said depositing is conducted prior to packaging of said MEMS device.

15. The process of claim 9 wherein said MEMS device includes an exposed surface, and wherein said exposed surface, excluding said bump area, comprises metallic material and wherein said anti-stiction coating comprises a material that is non-reactive with metallic material.

16. The process of claim 9 wherein said depositing is conducted at a pressure of approximately 900 millitorr.

17. The process of claim 9 wherein said anti-stiction coating is manufactured of a silane precursor, and wherein said silane is introduced to said deposition chamber at a partial pressure in a range of 100 to 300 millitorr.

18. The process of claim 9 wherein a catalyst is added to said deposition chamber during depositing of said anti-stiction coating.

19. The process of claim 18 wherein said catalyst is chosen from one of water and acetic acid.

20. The process of claim 18 wherein said catalyst is added as a vapor in an amount at least equal to an amount of vaporized anti-stiction precursor coating material.

21. The process of claim 9 wherein said depositing comprises a chemical reaction, and wherein said reaction is completed in a time period of less than twenty minutes at an ambient temperature.

22. The process of claim 9 further comprising, after said depositing, heating said MEMS device for a time period of greater than forty minutes and less than one hundred minutes at a temperature in a range of 100 to 120 degrees Celsius.

23. The process of claim 22 further comprising, prior to said heating, flushing said deposition chamber with an inert gas.

24. The process of claim 9 wherein the deposited anti-stiction coating has a thickness of at most twenty Angstroms.

25. The process of claim 9 wherein said MEMS device is pretreated prior to said depositing, said pretreatment comprising placing said MEMS device in an atmosphere chosen from one of a water plasma and an oxygen plasma.

26. The process of claim 9 wherein said MEMS device is pretreated prior to said depositing, said pretreatment comprising placing said MEMS device in an atmosphere chosen from benzoic acid, perfluorobenzoic acid, lauric acid, and perfluorooctanoic acid.

27. A process of depositing an anti-stiction coating, comprising:

positioning a microelectronic device for deposition, said microelectronic device including at least one bump region, said bump region comprising a dielectric material; and

reacting fluorodecyltrichlorosilane only on said bump region of said microelectronic device.

28. The process of claim 27 wherein said positioning comprises positioning a wafer for said reacting, said wafer including a plurality of said microelectronic devices each including at least one bump region, and wherein said selectively reacting comprises reacting said fluorodecyltrichlorosilane only on said bump region of said microelectronic devices.

29. The process of claim 27 further comprising, prior to said reacting, pretreating said bump region with one of a water plasma and an oxygen plasma.

30. The process of claim 27 further comprising, prior to said reacting, pretreating said bump region with a pretreatment material that generates SiOH groups on a surface of said bump region.

31. The process of claim 27 wherein said reacting takes place in a deposition chamber, said process further including adding a catalyst to said deposition chamber during said reacting, said catalyst chosen from one of water and acetic acid.

32. The process of claim 27 wherein said positioning a microelectronic device for deposition comprises placing said device in a sealed package together with said fluorodecyltrichlorosilane.