Method for embedding dies

• US 7,759,167 B2
• Filed: 11/21/2006
• Issued: 07/20/2010
• Est. Priority Date: 11/23/2005
• Status: Active Grant

• Current Assignee: Universiteit Gent Vzw
• Original Assignee: IMEC International, Universiteit Gent Vzw
• Inventors: Christiaens, Wim, Vanfleteren, Jan
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Lee; Jae
• Application Number:
  US11/602,733
• Publication Number:
  US 20070134849A1
• Time in Patent Office: 1,337 Days
• Field of Search: 438/106, 438/107, 438/110, 438/112, 438/113, 438/118, 438/125, 438/126, 438/127
• US Class Current: 438/118
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68322 Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82007 involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A method of manufacturing a semiconductor device is provided, involving forming a first flexible film on a rigid carrier substrate, attaching a die to the flexible film, so as to leave contacts on the die exposed, forming a wiring layer to contact the contacts of the die, and releasing the flexible film where the die is attached, from the carrier. An area of the first flexible film where the die is attached can have a lower adhesion to the rigid carrier substrate than other areas, so that releasing can involve cutting the first flexible film to release a part of the area of lower adhesion, and leaving an area of higher adhesion. A combined thickness of the die, the first flexible film and the wiring layer can be less than 150 μm, so that the device is bendable. Devices can be stacked.

Claims

1. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a first flexible film on a rigid carrier substrate;

thereafter

attaching a die to the first flexible film, wherein the die is positioned face-up on the first flexible film so as to leave contacts on the die exposed, and wherein a surface of the die attached to the first flexible film has no contacts;

thereafter

forming a wiring layer on the die to contact the contacts of the die while the die is attached to the first flexible film; and

thereafter

releasing the first flexible film from the rigid carrier substrate, wherein the first flexible film forms a part of a chip package.

2. The method of claim 1, further comprising steps of:

forming a second flexible film to cover the die after the die has been attached to the first flexible film; and

forming holes in the second flexible film to leave the contacts exposed.

3. The method of claim 2, wherein a combined thickness of the die, the first flexible film, the second flexible film, and the wiring layer is less than about 150 μ

m.

4. The method of claim 1, further comprising a step of gluing the die to the first flexible film.

5. The method of claim 1, wherein an area of the first flexible film where the die is attached has a lower adhesion to the rigid carrier substrate than another area of the first flexible film.

6. The method of claim 5, wherein the step of releasing comprises the step of cutting the first flexible film in the area of lower adhesion so as to release a part of the area of lower adhesion, and so as to leave an area of higher adhesion.

7. The method of claim 2, further comprising the steps of:

forming at least one recess in at least one of the first flexible layer and second flexible layer, and

situating the die in the recess.

8. The method of claim 1, wherein the first flexible film comprises a polyimide.

9. The method of claim 1, wherein the wiring layer comprises a fan-out of wires.

11. A method of manufacturing a stack, the method comprising the steps of:

manufacturing a plurality of semiconductor devices according to the method of claim 1; and

arranging the semiconductor devices in a stack with electrical connections between semiconductor devices in the stack.

12. The method of claim 11, further comprising a step of testing the semiconductor devices after manufacture and before arranging them into a stack.

13. A stack of semiconductor devices prepared according to the method of claim 11.

14. The method of claim 1, wherein the chip package is an ultra-thin chip package having a thickness of less than 150 μ

m.

16. The method of claim 14, wherein the die is a silicon chip having a thickness of from 20 μ

m to 30 μ

m.

10. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a first flexible film on a rigid carrier substrate, so that at least one area of the first flexible film has a lower adhesion to the rigid carrier substrate than another area of the flexible film;

thereafter

attaching a die to an area of the first flexible film having a lower adhesion to the carrier substrate, wherein the die is positioned face-up on the first flexible film, and wherein a surface of the die attached to the first flexible film has no contacts; and

thereafter

releasing the area of the first flexible film having a lower adhesion to the rigid carrier substrate from the carrier substrate, wherein the die and the area of the first flexible film having a lower adhesion to the rigid carrier substrate form a portion of a chip package.

15. The method of claim 10, wherein the chip package has a thickness of less than 150 μ

m.

17. The method of claim 15, wherein the die is a silicon chip having a thickness of from 20 μ

m to 30 μ

m.

18. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a first flexible film on a rigid carrier substrate;

thereafter

attaching a die to a portion of the first flexible film so as to leave contacts on the die exposed;

forming a wiring layer on the die to contact the contacts of the die; and

thereafter

releasing the portion of the first flexible film to which the die is attached from the rigid carrier substrate, wherein the die and the portion of the first flexible film form a portion of a chip package.

19. The method of claim 18, wherein the die is positioned face-up on the first flexible film.

20. The method of claim 18, wherein the step of forming a wiring layer to contact the contacts of the die is carried out while the die is attached to the first flexible film.

21. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a first flexible film on a rigid carrier substrate, so that at least one area of the first flexible film has a lower adhesion to the rigid carrier substrate than another area of the flexible film;

thereafter

attaching a die to an area of the first flexible film having a lower adhesion to the carrier substrate; and

thereafter

releasing the area of the first flexible film having a lower adhesion to the rigid carrier substrate from the carrier substrate, wherein the die and the area of the first flexible film having a lower adhesion to the rigid carrier substrate form a portion of a chip package.

22. The method of claim 21, wherein the die is positioned face-up on the first flexible film.