Semiconductor device and method of fabricating the same

• US 7,759,185 B2
• Filed: 09/11/2007
• Issued: 07/20/2010
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nam, Seo-woo, Moon, Young-joon, Lee, Nae-in, Shin, Hong-jae
• Primary Examiner(s): Monbleau; Davienne
• Assistant Examiner(s): MULCARE, SHWETA PRASAD
• Application Number:
  US11/853,187
• Publication Number:
  US 20080272436A1
• Time in Patent Office: 1,043 Days
• Field of Search: 438/197, 438/199, 438/287, 438/692, 438/216, 438/200, 438/218, 438/702, 438/637, 257/369, 257/E21.159, 257/E21.616, 257/E21.214, 257/E21.24, 257/E21.249, 257/E21.632
• US Class Current: 438/199
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a first stress film covering a first gate electrode and first source/drain areas of a first transistor area of a semiconductor substrate and at least a portion of a third gate electrode of an interface area between the first transistor area and a second transistor area;

forming a second stress film covering a second gate electrode and second source/drain areas of the second transistor area of the semiconductor substrate and overlapping at least a portion of the first stress film on the third gate electrode of the interface area;

forming an interlayer insulating film on the semiconductor substrate;

patterning the interlayer insulating film to form a plurality of preliminary contact holes through which the first stress film on the first gate electrode and the first source/drain areas and the second stress film on the second and the third gate electrodes and the second source/drain areas are exposed;

filling the plurality of preliminary contact holes with a filling material;

removing the filling material to expose the second stress film in the interface area while the filling material remains in the preliminary contact holes of the first transistor area and the second transistor area;

removing the exposed second stress film of the interface area;

removing the remaining filling material to expose the first stress film of the first transistor area and the second stress film of the second transistor area; and

removing the exposed first stress film and second stress film to form a plurality of contact holes through which the first, the second, and the third gate electrodes, and the first and the second source/drain areas are exposed.

2. The method of claim 1, wherein:

the filling material is formed of an organic material; and

the removing of the filling material is performed using an etchback process or an ashing process.

3. The method of claim 2, wherein the organic material is a polyarylene ether-based material, a polymethamethylacrylate-based material, or a vinylether methacrylate-based material.

4. The method of claim 1, wherein:

the filling material is formed of an inorganic material; and

the removing of the filling material is performed using a wet etching process.

5. The method of claim 4, wherein the inorganic material is an HSQ-based material (hydrogensilsesquioxane-based material) or an MSQ-based material (methyl silsesquioxane-based material).

6. The method of claim 1, wherein:

the plurality of contact holes are formed in recessed portions of the first, the second, and the third gate electrodes and the first and the second source/drain areas; and

a depth of the recessed portion in the interface area is larger than a depth of the recessed portion in the first transistor area or the second transistor area.

7. The method of claim 1, wherein:

a first transistor is an n-channel metal oxide semiconductor (NMOS) transistor; and

a second transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

8. The method of claim 7, wherein:

the first stress film has tensile stress of about 0.01 to about 5 GPa; and

the second stress film has compressive stress of about −

0.01 to about −

5 GPa.

9. The method of claim 1, wherein the first stress film and the second stress film are formed of silicon nitride (SiN), silicon oxynitride (SiON), silicon boron nitride (SiBN), silicon carbide (SiC), hydrogenated silicon carbide (SiC:

H), hydrogenated silicon oxycarbide (SiCOH), silicon carbon nitride (SiCN), silicon dioxide (SiO₂), or a combination thereof.

10. The method of claim 9, wherein the first stress film and the second stress film are about 1 to about 1000 angstroms (Å

) in thickness.

11. The method of claim 10, wherein a thickness of the first stress film is substantially the same as a thickness of the second stress film.

12. The method of claim 1, further comprising:

forming an etch stop film on the first stress film;

wherein the removing of the first stress film of the interface area includes removing the etch stop film and the first stress film.

13. The method of claim 12, wherein the second stress film is thicker than the first stress film.

14. The method of claim 1, wherein the first, the second, and the third gate electrodes and the first and the second source/drain areas have upper sides including silicide films.

15. The method of claim 1, wherein the interlayer insulating film is formed of tetra ethyl ortho silicate (TEOS), (ozone)O₃-(tetra ethyl ortho silicate) TEOS, silicon dioxide (SiO₂), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or a combination thereof.