Method of forming lateral trench MOSFET with direct trench polysilicon contact

• US 7,759,200 B2
• Filed: 04/29/2009
• Issued: 07/20/2010
• Est. Priority Date: 08/28/2006
• Status: Expired due to Fees

• Current Assignee: Advanced Analogic Technologies Hong Kong Ltd (Skyworks Solutions Incorporated), Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Hong Kong Ltd (Skyworks Solutions Incorporated), Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Disney, Donald Ray, Ma, Cho Chiu
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): MCCALL SHEPARD, SONYA D
• Application Number:
  US12/387,180
• Publication Number:
  US 20090215237A1
• Time in Patent Office: 447 Days
• Field of Search: 438/270, 257/E27.015
• US Class Current: 438/270
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched.

Claims

1. A method of forming a lateral trench MOSFET comprising:

forming a trench in a semiconductor substrate, the trench comprising an LTDMOS segment and a gate bus segment;

lining the walls of the trench with a dielectric layer;

introducing a first conductive material into the trench;

implanting a dopant of a first conductivity type into the substrate to form a body region adjacent a sidewall of the LTDMOS segment of the trench;

implanting a dopant of a second conductivity type into the substrate to form a drift region adjacent the body region and the sidewall of the LTDMOS segment of the trench;

implanting a dopant of the second conductivity type into the substrate to form a source region adjacent a top surface of the substrate and the body region;

implanting a dopant of the second conductivity type into the substrate to form a drain region adjacent the top surface of the substrate laterally spaced apart from the source region;

forming a second dielectric layer over the top surface of the substrate;

forming a contact hole in the second dielectric layer above the gate bus segment of the trench, the contact hole having substantially vertical walls which intersect the conductive material in the gate bus segment of the trench;

filling the contact hole with a second conductive material to form a contact plug in the contact hole; and

forming a gate metal layer over the second dielectric layer, the gate metal layer being in contact with the contact plug.

2. The method of claim 1 comprising planarizing the top surfaces of the substrate and the first conductive material.

3. The method of claim 1 wherein filling the contact hole with a conductive material comprises filling the contact hole with tungsten.

4. The method of claim 2 comprising forming and removing a protective layer over the substrate before the formation of the source and drain regions.