Memory cell array comprising wiggled bit lines

• US 7,759,704 B2
• Filed: 10/16/2008
• Issued: 07/20/2010
• Est. Priority Date: 10/16/2008
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Schloesser, Till, Popp, Martin
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): KUO, WENSING W
• Application Number:
  US12/252,853
• Publication Number:
  US 20100096669A1
• Time in Patent Office: 642 Days
• Field of Search: 257/296, 257390-392, 257/202, 257/208, 257E27084-E27086
• US Class Current: 257/208
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.

Claims

1. An integrated circuit including a memory cell array comprising:

transistors arranged along parallel continuous active area lines;

bitlines arranged such that individual ones of the bitlines intersect a plurality of the continuous active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines; and

wordlines arranged so that individual ones of the wordlines intersect a plurality of the continuous active area lines, and individual ones of the wordlines intersect a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to a same continuous active area line, are connected with different bitlines;

wherein the bitlines generally extend along a first direction;

wherein the wordlines extend along a second direction, the second direction being perpendicular to the first direction; and

wherein the continuous active area lines extend in a direction that is slanted with respect to the first and second directions.

2. The integrated circuit according to claim 1, wherein the active area lines are straight lines.

3. The integrated circuit according to claim 1, wherein the memory cell array further comprises storage capacitors.

4. The integrated circuit according to claim 3, wherein the storage capacitors are formed over a surface of a semiconductor substrate.

5. The integrated circuit according to claim 1, wherein one bitline-contact is associated with two neighboring transistors that are assigned to one active area line.

6. The integrated circuit of claim 1, wherein the bitline-contacts that are associated with neighboring bitlines are arranged along one line, this line generally extending along the second direction.

7. The integrated circuit of claim 1, further comprising capacitor contacts that are configured to connect the transistors with corresponding capacitors, wherein the capacitor contacts are disposed along lines extending in the second direction.

8. The integrated circuit according to claim 1, wherein the wordlines are formed as buried wordlines.

9. The integrated circuit of claim 1, further comprising isolation gatelines which are adapted to isolate neighboring transistors from each others, the isolation gatelines being arranged in parallel with the wordlines.

10. An integrated circuit including a memory cell array comprising:

bitlines formed as wiggled lines, the bitlines generally extending along a first direction;

wordlines running along a second direction, the second direction being perpendicular to the first direction;

continuous active area lines, transistors being formed in the active area lines, the active area lines extending in a direction that is slanted with respect to the first and second directions; and

bitline contacts disposed in regions generally defined by an intersection of a bitline and a corresponding continuous active area line;

wherein neighboring bitline contacts that are shifted along a direction that is slanted with respect to the first and second directions, respectively, and that are disposed in regions corresponding to a same continuous active area line, are connected with neighboring bitlines.

11. The integrated circuit according to claim 10, wherein the active area lines are straight lines.

12. The integrated circuit according to claim 10, wherein the memory cell array further comprises storage capacitors.

13. The integrated circuit according to claim 12, wherein the storage capacitors are formed over a surface of a semiconductor substrate.

14. The integrated circuit according to claim 10, wherein one bitline contact is associated with two neighboring transistors that are assigned to one active area line.

15. The integrated circuit of claim 10, wherein the bitline-contacts that are associated with neighboring bitlines are arranged along one line, this line generally extending along the second direction.

16. The integrated circuit of claim 10, further comprising capacitor contacts that are configured to connect the transistors with corresponding capacitors, wherein the capacitor contacts are disposed along lines extending in the second direction.

17. The integrated circuit according to claim 10, wherein the wordlines are formed as buried wordlines.

18. The integrated circuit of claim 10, further comprising isolation gatelines which are adapted to isolate neighboring transistors from each others, the isolation gatelines being arranged in parallel with the wordlines.