Memory cell array comprising wiggled bit lines
First Claim
Patent Images
1. An integrated circuit including a memory cell array comprising:
- transistors arranged along parallel continuous active area lines;
bitlines arranged such that individual ones of the bitlines intersect a plurality of the continuous active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines; and
wordlines arranged so that individual ones of the wordlines intersect a plurality of the continuous active area lines, and individual ones of the wordlines intersect a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to a same continuous active area line, are connected with different bitlines;
wherein the bitlines generally extend along a first direction;
wherein the wordlines extend along a second direction, the second direction being perpendicular to the first direction; and
wherein the continuous active area lines extend in a direction that is slanted with respect to the first and second directions.
3 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.
-
Citations
18 Claims
-
1. An integrated circuit including a memory cell array comprising:
-
transistors arranged along parallel continuous active area lines; bitlines arranged such that individual ones of the bitlines intersect a plurality of the continuous active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines; and wordlines arranged so that individual ones of the wordlines intersect a plurality of the continuous active area lines, and individual ones of the wordlines intersect a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to a same continuous active area line, are connected with different bitlines; wherein the bitlines generally extend along a first direction; wherein the wordlines extend along a second direction, the second direction being perpendicular to the first direction; and wherein the continuous active area lines extend in a direction that is slanted with respect to the first and second directions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. An integrated circuit including a memory cell array comprising:
-
bitlines formed as wiggled lines, the bitlines generally extending along a first direction; wordlines running along a second direction, the second direction being perpendicular to the first direction; continuous active area lines, transistors being formed in the active area lines, the active area lines extending in a direction that is slanted with respect to the first and second directions; and bitline contacts disposed in regions generally defined by an intersection of a bitline and a corresponding continuous active area line; wherein neighboring bitline contacts that are shifted along a direction that is slanted with respect to the first and second directions, respectively, and that are disposed in regions corresponding to a same continuous active area line, are connected with neighboring bitlines. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
Specification