Electrically alterable memory cell

• US 7,759,719 B2
• Filed: 05/02/2005
• Issued: 07/20/2010
• Est. Priority Date: 07/01/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Primary Examiner(s): Lee; Eugene
• Application Number:
  US11/120,691
• Publication Number:
  US 20060006454A1
• Time in Patent Office: 1,905 Days
• Field of Search: 257/E29.303, 257/E29.305, 257/E29.306, 257/E29.309, 257314-316, 257/319, 257/320, 257/324, 257/29
• US Class Current: 257/314
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A nonvolatile memory cell is provided. The cell has a charge filter, a tunneling gate, a ballistic gate, a charge storage layer, a source, and a drain with a channel defined between the source and drain. The charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage layer while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. Further embodiments of the present invention provide a cell having a charge filter, a supplier gate, a tunneling gate, a ballistic gate, a source, a drain, a channel, and a charge storage layer. The present invention further provides an energy band engineering method permitting the memory cell be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Claims

1. A nonvolatile memory cell, comprising:

a body of a semiconductor material having a first conductivity type;

first and second spaced-apart regions formed in the body and having a second conductivity type, with a channel region of the body defined between the first and second spaced-apart regions;

a charge storage layer disposed over and insulated from the channel region;

a ballistic gate disposed over and insulated from the charge storage layer; and

a tunneling gate disposed over and insulated from the ballistic gate by a charge filter,

wherein the charge filter (i) permits transporting of charge carriers of one polarity type from the tunneling gate through the ballistic gate to the charge storage layer and (ii) blocks transporting of charge carriers of an opposite polarity type from the ballistic gate to the tunneling gate,

wherein the charge filter comprises;

a first dielectric disposed adjacent to the ballistic gate; and

a second dielectric disposed adjacent to the first dielectric, wherein the first dielectric has an energy band gap narrower than an energy band gap of the second dielectric, and

wherein the tunneling gate comprises a p+ semiconductor and the ballistic gate comprises an n+ semiconductor having an energy band gap narrower than an energy band gap of the first dielectric.

2. The memory cell of claim 1, wherein a product of a dielectric constant of the first dielectric and a thickness of the second dielectric is substantially greater than a product of a dielectric constant of the second dielectric and a thickness of the first dielectric.

3. The memory cell of claim 1, wherein the second dielectric comprises oxide, and the first dielectric comprises material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

4. The memory cell of claim 1, wherein the second dielectric comprises oxynitride, and the first dielectric comprises material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

5. The memory cell of claim 1, wherein the ballistic gate has a Fermi level in a flat band condition that lies nominally in the middle of the energy band gap of the first dielectric.

6. The memory cell of claim 1, wherein the tunneling gate emits hole carriers when positively biased with respect to the ballistic gate, and emits electron carriers when negatively biased with respect to the ballistic gate.

7. The memory cell of claim 1, wherein the ballistic gate comprises material selected from the group consisting of Pt, Au, W, Mo, Ru, Ta, TaN, TiN, n+ polysilicon, p+ polysilicon, n+ poly SiGe and p+ poly SiGe.

8. The memory cell of claim 1, wherein the charge storage layer comprises polysilicon.

9. The memory cell of claim 1, wherein the charge storage layer comprises a dielectric having a plurality of charge storing traps.