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Electronic circuit chip, and electronic circuit device and method for manufacturing the same

  • US 7,759,786 B2
  • Filed: 10/05/2006
  • Issued: 07/20/2010
  • Est. Priority Date: 10/07/2005
  • Status: Expired due to Fees
First Claim
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1. A method for manufacturing an electronic circuit device, comprising:

  • preparing a first electronic circuit chip, said first electronic circuit chip comprising;

    an insulating layer provided as a surface layer;

    a patterned conductor provided in said insulating layer, said patterned conductor comprising a first metallic material and having a portion that is exposed in a surface of said insulating layer, said exposed portion of said patterned conductor being coplanar with said surface of said insulating layer; and

    a metallic film provided on a first portion of said exposed portion of said patterned conductor, said metallic film comprising a second metallic material which requires a free energy for forming an oxide that is higher than a free energy for forming an oxide that is required by said first metallic material;

    preparing a second electronic circuit chip that includes a resin layer provided in a surface layer and a solder layer provided in said resin layer and exposed in a surface of said resin layer; and

    connecting said metallic film of said first electronic circuit chip and said solder layer of said second electronic circuit chip by heating said solder layer, while said solder layer is pressed against said metallic film,wherein said preparing said first electronic circuit chip comprises;

    forming a Cu film on a silicon wafer serving as a support substrate;

    forming a plurality of external electrode pads on said Cu film;

    forming a first insulating resin layer on said Cu film and covering said external electrode pads, said first insulating resin layer comprising one of polyimide resin and epoxy resin;

    exposing a top surface of said plurality of external electrode pads;

    forming a plurality of lower conductor interconnects on said first insulating resin layer, said forming said plurality of lower conductor interconnects comprising connecting said lower conductor interconnects to said external electrode pads;

    forming a plurality of via plugs on said plurality of lower conductor interconnects, said forming said plurality of via plugs comprising connecting said via plugs to said plurality of lower conductor interconnects;

    forming a second insulating resin layer on said first insulating resin layer, said forming said second insulating resin layer comprising covering said plurality of lower conductor interconnects and said via plugs with said second insulating resin layer;

    exposing top surfaces of said via plugs;

    forming upper conductor interconnect on said second insulating resin layer;

    forming said insulating layer in said upper conductor interconnect, said insulating layer being coplanar with said upper conductor interconnect, said patterned conductor comprising said plurality of lower conductor interconnects and said upper conductor interconnect;

    exposing a top surface of said insulating layer;

    forming a resist layer on a first portion of said upper conductor interconnect on which a metal oxide film will be formed and on said insulating layer;

    forming said metallic film on a second portion of said upper conductor interconnect not covered by said resist layer;

    removing said resist layer; and

    forming said metal oxide film on said first portion of said upper conductor interconnect, said metal oxide film comprising an oxide of said first metallic material.

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