Vertically integrated transceiver array

• US 7,760,142 B2
• Filed: 04/10/2007
• Issued: 07/20/2010
• Est. Priority Date: 04/10/2007
• Status: Expired due to Fees

• Current Assignee: EMAG Technologies, Inc.
• Original Assignee: EMAG Technologies, Inc.
• Inventors: Sabet, Kazem F., Katehi, Linda P. B., Margomenos, Alexandros
• Primary Examiner(s): MANCUSO, HUEDUNG XUAN CAO
• Application Number:
  US11/733,564
• Publication Number:
  US 20080252521A1
• Time in Patent Office: 1,197 Days
• Field of Search: 343/700.MS, 343/770, 343/702, 343/846, 343/848, 343/853, 342/368
• US Class Current: 343/700.0MS
• CPC Class Codes: H01Q 21/0025 Modular arrays

Abstract

A transceiver array that employs vertically integrated circuits in one or more wafers. The array includes a digital wafer having digital circuits. A plurality of RF cubes are formed to the digital wafer, where each RF cube includes an antenna wafer and at least one lower wafer, and where each RF cube represents a separate channel of the array. The antenna wafer includes a patch antenna and a resonating cavity. The at least one lower wafer includes high frequency RF integrated circuits and intermediate frequency RF integrated circuits. The array has application as a front-end for a digital beam-forming system.

Claims

1. A transceiver array comprising:

a digital wafer including digital integrated circuits; and

a plurality of RF cubes formed to the digital wafer, each of the RF cubes including a plurality of integrated circuit wafers “

including”

wherein the plurality of integrated circuit wafers include an antenna wafer and at least one lower wafer, said antenna wafer including an antenna and a resonating cavity and said lower wafer including a least one integrated circuit.

2. The array according to claim 1 wherein the at least one lower wafer includes high frequency integrated MMIC circuits.

3. The array according to claim 2 wherein the high frequency integrated MMIC circuits include low-noise amplifiers, band-pass filters and mixers.

4. The array according to claim 3 wherein the low-noise amplifiers and the band-pass filters include a MEMS tunable matching network.

5. The array according to claim 2 wherein the high frequency integrated MMIC circuits include a microelectro-mechanical switch.

6. The array according to claim 1 wherein the at least one lower wafer includes intermediate frequency integrated circuits.

7. The array according to claim 6 wherein the intermediate frequency integrated circuits include amplifiers and band-pass filters.

8. The array according to claim 7 wherein the amplifiers and band-pass filters include a MEMS tunable matching network.

9. The array according to claim 1 wherein the at least one lower wafer is a first lower wafer that covers the resonating cavity and a second lower wafer that is provided between the first lower wafer and the digital wafer.

10. The array according to claim 1 wherein each of the plurality of the RF cubes includes at least one evanescent mode filter.

11. The array according to claim 10 wherein the evanescent mode filter is tunable.

12. The array according to claim 1 wherein the digital integrated circuits include analog-to-digital converters and digital-to-analog converters.

13. The array according to claim 1 wherein the antenna is selected from the group consisting of patch antennas, printed dipole antennas, slot antennas, spiral antennas, loop antennas, planar inverted F antennas and Vivaldi antennas.

14. The array according to claim 1 wherein the antenna wafer and the at least one lower wafer are silicon wafers.

15. The array according to claim 1 wherein the digital wafer is a CMOS wafer.

16. The array according to claim 1 wherein the digital wafer is a printed circuit board carrier.

17. The array according to claim 1 further comprising weighting junctions and a digital beam-forming processor provided on the digital wafer.

18. The array according to claim 1 wherein the antenna is both linearly and circularly polarized.

19. A vertically integrated RF circuit comprising:

an antenna wafer having a first surface and a second surface, said antenna wafer including an antenna formed to the first surface and a resonating cavity formed through the second surface;

a first RF wafer covering the resonating cavity and including at least one integrated circuit; and

a second RF wafer electrically coupled to the first RF wafer, said second RF wafer including at least one integrated circuit.

20. The integrated RF circuit according to claim 19 wherein the first RF wafer includes high frequency integrated circuits and the second RF wafer includes intermediate frequency integrated circuits.

21. The integrated RF circuit according to claim 19 wherein the antenna is a patch antenna.

22. The array according to claim 19 wherein the high frequency integrated MMIC circuits include an RF microelectro-mechanical switch.

23. The array according to claim 19 wherein each of the plurality of the RF cubes includes an evanescent mode filter.

24. The array according to claim 23 wherein the evanescent mode filter is tunable.

25. The integrated RF circuit according to claim 19 wherein the integrated RF circuit is a channel in a transceiver array.

26. The integrated RF circuit according to claim 25 wherein the transceiver array is a digital beam-forming transceiver array.

27. The array according to claim 19 wherein the antenna wafer and the first and second wafers are silicon wafers.

28. A transceiver array that provides digital beam-forming for both transmit and receive signals, said transceiver array comprising:

a digital wafer including analog-to-digital converters, digital-to-analog converters, weighting junctions and a digital beam-forming processor; and

a plurality of RF cubes formed to the digital wafer where each RF cube is a channel in the array, each of the RF cubes including an antenna wafer, a first lower wafer and a second lower wafer, said antenna wafer including a patch antenna and a resonating cavity, said first lower wafer covering the resonating cavity and including high frequency RF MMIC integrated circuits and said second lower wafer including intermediate frequency integrated MMIC circuits.

29. The array according to claim 28 wherein the antenna wafer and the first and second lower wafers are silicon wafers.

30. The array according to claim 28 wherein the digital wafer is a CMOS wafer.

31. The array according to claim 28 wherein the antenna is both linearly and circularly polarized.