Design-based method for grouping systematic defects in lithography pattern writing system

• US 7,760,347 B2
• Filed: 05/15/2006
• Issued: 07/20/2010
• Est. Priority Date: 05/13/2005
• Status: Active Grant

• Current Assignee: Applied Materials Israel Limited (Applied Materials Incorporated)
• Original Assignee: Applied Materials Incorporated
• Inventors: Orbon, Jacob J. Jr., Shishi, Rinat, Ben-Porath, Ariel, Almogy, Gilad, Svidenko, Vicky, Nehmadi, Youval, Ravid, Erez, Bokobza, Ofer
• Primary Examiner(s): Chowdhury; Tarifur
• Assistant Examiner(s): PAJOOHI GOMEZ, TARA S
• Application Number:
  US11/383,395
• Publication Number:
  US 20060269120A1
• Time in Patent Office: 1,527 Days
• Field of Search: 3562371-2376, 356/237.4, 382141-145
• US Class Current: 356/237.4
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects

Abstract

Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.

Claims

1. A method for identifying defects in fabrication of a semiconductor wafer, comprising:

determining locations of some defects on the semiconductor wafer;

determining if a set of defect areas, each surrounding a different one of the defects, contains one or more common circuit structural elements;

if one or more common circuit structural elements are identified, categorizing the defects surrounded by the set of defect areas as corresponding to the common circuit structural elements;

selecting a subset of defects categorized as corresponding to the matched common circuit structural elements for sampling; and

matching the common circuit structural element in similar defected neighborhoods in different locations across the wafer to identify defects associated with the common circuit structural element.

2. The method of claim 1, further comprising:

providing, in a graphical format, an indication of different numbers of defects categorized as corresponding to different sets of one or more common circuit structural elements.

3. The method of claim 1, wherein selecting the subset of defects comprises automatically selecting a limited number of the defects categorized as corresponding to the matched common circuit structural elements for sampling under program control.

4. The method of claim 1, wherein selecting the subset of defects comprises automatically selecting a limited number of the defects categorized as corresponding to the matched common circuit structural elements for sampling, based on one or more criteria specified by a user.

5. The method of claim 1, wherein determining locations of defects on the semiconductor wafer comprises aligning a defect map generated via an inspection tool to a computer automated design (CAD) model of the wafer in a graphics form.

6. The method of claim 1, wherein matching the common circuit structural element in similar defected neighborhoods in different locations across the wafer comprises generating and aligning one or more area maps including areas surrounding each defect.

7. The method of claim 6, wherein aligning one or more area maps comprises determining if the common circuit structural element in one area map can be aligned, within a predetermined distance, with the common circuit structural element in another area map.