Programmable pseudo virtual lanes for fibre channel systems

• US 7,760,752 B2
• Filed: 06/18/2008
• Issued: 07/20/2010
• Est. Priority Date: 07/21/2003
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Dropps, Frank R., Ross, Edward C.
• Primary Examiner(s): Levitan; Dmitry H
• Application Number:
  US12/141,519
• Publication Number:
  US 20080310306A1
• Time in Patent Office: 762 Days
• Field of Search: 370/241, 370/242, 370/252, 370/389, 370/400, 370/412, 370/429, 370/437, 370/465, 370/477, 370/503, 709/228, 709/237, 709/238
• US Class Current: 370/437
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/506 Backpressure

Abstract

A method and switch element for assigning priority to pseudo virtual lanes (“PVL”) using a fibre channel switch element is provided. The method includes, assigning received R_RDYs based on a PVL distribution scheme; and determining traffic congestion on a PVL if there is no credit available to transfer frames from the PVL. A minimum bandwidth feature is enabled to avoid lower priority PVLs from getting no credit for transmitting frames; and distributing credit and R_RDYs based on frame age bits, wherein a lower priority PVL gets credit if a frame is waiting in the PVL for a longer duration compared to a higher priority PVL. The switch element includes, a PVL module having credit counters for plural PVLs; and a timer that monitors frame traffic for each PVL lane. If a PVL gets congested, then a state machine adjusts priority of R_RDY distribution scheme of other PVLs to transmit frames.

Claims

1. A switch element having a plurality of ports, each port having a receive segment and a transmit segment for routing frames, comprising:

a plurality of pseudo virtual lanes (PVLs) for transmitting frames, where each PVL is assigned a configurable initial priority for transmitting frames when credit is available at a receive segment of another port for receiving a frame;

a first storage module for storing a configurable threshold value for each PVL that determines a number of credits that are allocated for each PVL before credit allocation for the PVL is modified;

a second storage module for storing a configurable maximum credit value assigned to each of the PVL and at any given time, credit is assigned to a PVL if the maximum credit value has not been reached;

a credit monitoring module for monitoring the threshold value and the maximum credit value for modifying a priority of the plurality of PVLs when credit is received for transmitting a frame;

a timer module that monitors frame traffic for each PVL and if a PVL stops transmitting frames beyond a certain programmable duration, then an indicator is set indicating that the PVL is congested so that priority for the congested PVL can be lowered; and

a minimum bandwidth module for providing a minimum bandwidth level for all the PVLs, which when enabled, bypasses credit assignment for the plurality of PVLs based on assigned priority, and instead assigns available credit to a PVL that was a last PVL to have been assigned credit.

2. The switch element of claim 1, wherein if a higher priority PVL gets congested as indicated by the timer module, then a state machine lowers the priority of the higher priority PVL and increases the priority of another PVL that is not congested so that available credit can be assigned to the uncongested PVL.

3. The switch element of claim 2, wherein if traffic congestion for the higher priority PVL is not relieved within a programmable duration, then the minimum bandwidth module is enabled to allocate credit to a lower priority PVL based on age bits used for indicating when a PVL was assigned credit.

4. The switch element of claim 1, wherein the first storage module is a register for storing the threshold value.

5. The switch element of claim 1, wherein the second storage module is a register for storing the maximum credit value.

6. The switch element of claim 1, wherein the bandwidth module is enabled when congestion for the PVLs is not relieved by modifying PVL priority.

7. The switch element of claim 1, wherein as a default, a PVL with a highest priority is granted available credit until credit assigned to the highest priority PVL within a given duration reaches the maximum credit value.

8. A system, comprising:

a first switch element enabled for using a plurality of pseudo virtual lanes (PVLs) for transmitting frames; and

a second switch element communicating with the first switch element without using PVLs;

wherein the first switch element comprises;

a first storage module for storing a configurable threshold value for each PVL that determines a number of credits that are allocated for each PVL before credit allocation for the PVL is modified;

a second storage module for storing a configurable maximum credit value assigned to each of the PVL and at any given time, credit is assigned to a PVL if the maximum credit value has not been reached;

a credit monitoring module for monitoring the threshold value and the maximum credit value for modifying a priority of the plurality of PVLs when credit is received for transmitting a frame;

a timer module that monitors frame traffic for each PVL and if a PVL stops transmitting frames beyond a certain programmable duration, then an indicator is set indicating that the PVL is congested such that priority for the congested PVL can be lowered; and

a minimum bandwidth module for providing a minimum bandwidth level for all the PVLs, which when enabled, bypasses credit assignment for the plurality of PVLs based on assigned priority, and instead assigns available credit to a PVL that was a last PVL to have been assigned credit.

9. The system of claim 8, wherein if a higher priority PVL gets congested as indicated by the timer module, then a state machine lowers the priority of the higher priority PVL and increases the priority of another PVL that is not congested so that available credit can be assigned to the uncongested PVL.

10. The system of claim 9, wherein if traffic congestion for the higher priority PVL is not relieved within a programmable duration, then the minimum bandwidth module is enabled to allocate credit to a lower priority PVL based on age bits used for indicating when a PVL was assigned credit.

11. The system of claim 8, wherein the first storage module is a register for storing the threshold value based on which credit allocation for a PVL is modified.

12. The system of claim 8, wherein the second storage module is a register for storing the maximum credit value based on which credit allocation for a PVL is modified.

13. The system of claim 8, wherein the bandwidth module is enabled when congestion for the PVLs is not relieved by modifying PVL priority.

14. The system of claim 8, wherein as a default, a PVL with a highest priority is granted available credit until credit assigned to the highest priority PVL within a given duration reaches the maximum credit value.

15. A switch element having a plurality of ports, each port having a receive segment and a transmit segment for routing frames, comprising:

a plurality of pseudo virtual lanes (PVLs) for transmitting frames, each PVL assigned a configurable initial priority for transmitting frames when credit is available at a receive segment of another port for receiving a frame;

wherein as a default, a PVL with a highest priority is granted available credit until credit assigned to the highest priority PVL within a given duration reaches a maximum credit value;

a timer module for monitoring frame traffic for each PVL and if a PVL stops transmitting frames beyond a certain programmable duration, then an indicator is set indicating that the PVL is congested so that priority for the congested PVL can be lowered; and

a minimum bandwidth module for providing a minimum bandwidth level for all the PVLs;

wherein the bandwidth module is enabled when congestion for the PVL is not relieved within a programmable duration and when enabled, available credit is allocated to a PVL that was a last PVL to have been assigned credit, instead of allocating credit based on assigned PVL priority.

16. The switch element of claim 15, wherein the switch elements communicates with another switch element that does not use PVLs.

17. The switch element of claim 16, wherein if traffic congestion for the higher priority PVL is not relieved within a programmable duration, then the minimum bandwidth module is enabled to allocate credit to a lower priority PVL based on age bits used for indicating when a PVL was assigned credit.

18. The switch element of claim 15, wherein if a higher priority PVL gets congested as indicated by the timer module, then a state machine lowers the priority of the higher priority PVL and increases the priority of another PVL that is not congested so that available credit can be assigned to the uncongested PVL.

19. The switch element of claim 15, wherein the switch element routes Fibre Channel frames.