Multi-threaded DMA

• US 7,761,617 B2
• Filed: 03/17/2005
• Issued: 07/20/2010
• Est. Priority Date: 10/11/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kolli, Praveen, Khalifa, Nabil, Ayinala, Sivayya, Atluri, Prabha, Seigneret, Franck
• Primary Examiner(s): Patel; Niketa I
• Application Number:
  US11/082,564
• Publication Number:
  US 20060080478A1
• Time in Patent Office: 1,951 Days
• Field of Search: 710/22, 710/23, 710/24, 710/35
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.

Claims

1. A direct memory access (DMA) circuit, comprising:

a read port;

a read port scheduler coupled to the read port;

a write port;

a write port scheduler coupled to the write port;

a request port coupled to the read and write port schedulers;

thread circuitry for holding next access addresses, wherein the read port is configured to support “

m”

threads and the write port is configured to support “

n”

threads, where each thread is configured to support a single access and a burst access transaction and the read and write ports are configured to work on different data transfers at the same time; and

channel context circuitry interconnected with the read port, write port and thread circuitry for storing channel context, wherein the channel context circuitry is configured to instantiate a plurality of virtual channels in excess of the number of threads, such that a free thread is associated with a selected virtual channel to initiate an access and then released.

2. The DMA circuit as defined in claim 1, wherein the read port scheduler and write port scheduler each arbitrate between the plurality of channels at a thread boundary.

3. The DMA circuit as defined in claim 1, wherein the read port and the write port scheduler each includes a high priority queue for high priority channels and a low priority queue for regular priority channels.

4. The DMA circuit as defined in claim 1, further comprising:

a memory coupled to the read and write ports; and

a configuration port coupled to the memory for receiving configuration information for configuring the DMA circuit.

5. The DMA circuit as defined in claim 2, wherein the context circuitry further comprises:

a channel context memory shared between the channels.

6. The DMA circuit as defined in claim 1, further comprising:

a read port response manager coupled to the read port; and

a write port response manager coupled to the write port.

7. The DMA circuit as defined in claim 6, wherein the read response manager is configured to identify the channel that owns particular data.

8. The DMA circuit as defined in claim 1, further comprising:

a first-in-first-out (FIFO) memory coupled to the read and write ports.

9. The DMA circuit as defined in claim 8, wherein the DMA provides for multithreaded DMA transfers, allowing for concurrent channel transfers.

10. The DMA circuit as defined in claim 9, further comprising:

an address alignment control coupled to the FIFO memory, the address alignment control allows for any source byte on any read port byte lane to be transferred to any write port byte lane.

11. The DMA circuit as defined in claim 10, further comprising an endianness conversion circuit coupled to the read port.

12. A multithreading direct memory access (DMA) circuit comprising:

a write port;

a read port;

a number of address circuits coupled to the read port and to the write port for holding addresses of a plurality of requests;

a context memory coupled to both the read and write ports for holding contexts of logical channels; and

a means coupled to the context memory for mapping requests to the address circuitry and to the logical channels, wherein the means is configured to instantiate a plurality of logical channels in excess of the number of address circuits.

13. The multithreading DMA circuit as defined in claim 12, wherein the means for mapping requests and logical channels is programmable.

14. The multithreading DMA circuit as defined in claim 12, wherein the read and write ports configured to work on different data transfers at the same time.

15. The multithreading DMA circuit as defined in claim 12, further comprising:

a read scheduler coupled to the read port; and

a write scheduler coupled to the write port, the read and write schedulers are decoupled with respect to each other.

16. The multithreading DMA circuit as defined in claim 15, wherein the read and write schedulers each have a first queue for high priority channels and a second queue for low priority channels.

17. The multithreading DMA circuit as defined in claim 16, wherein the arbitration between the two queues in each of the read and write schedulers is performed according to a parameter providing the number of times the high priority channel grants a port before the low priority channel wins the port.

18. The multithreading DMA circuit as defined in claim 12, wherein the channel context memory is shared by all of the logical channels.

19. The multithreading DMA circuit as defined in claim 18, further comprising a read port response manger coupled to the read port that includes a packing control for adjusting the channel element type to the read port.

20. A method of operating a multi-threaded direct memory access (DMA) circuit, comprising:

instantiating a plurality “

v”

of virtual channels, wherein each virtual channel identifies a source and destination address for transferring a sequence of data from one storage location to a different storage location;

selecting a subset “

s”

of the plurality of virtual channels via arbitration, where s is less than v;

mapping the selected virtual channels onto physical thread circuits to form a plurality of requests;

queuing the requests to perform either a single access or a burst access; and

releasing each thread circuit at the completion of the associated request access for use by another selected virtual channel.