Serialization of data for communication with slave in multi-chip bus implementation

• US 7,761,632 B2
• Filed: 04/27/2007
• Issued: 07/20/2010
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Bracamontes Del Toro, Rocendo
• Primary Examiner(s): Shin; Christopher B
• Application Number:
  US11/741,250
• Publication Number:
  US 20080270655A1
• Time in Patent Office: 1,180 Days
• Field of Search: 710105-110, 710/100, 710/300, 710305-307, 710316-317, 710 25- 29, 710 33- 35, 710 58- 61, 710/71
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 2213/0038 System on Chip

Abstract

Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.

Claims

1. A serializer for interfacing bus communications for a slave in a bus system, the serializer comprising:

one or more shift registers operative to serialize information to send over a communication bus and deserialize information received from a communication bus; and

a mechanism coupled to the shift registers and operative to provide parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, wherein the mechanism is operative to provide deserialized information received from the shift registers to a bus matrix, and wherein the mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.

2. The serializer of claim 1 wherein the mechanism is a finite state machine.

3. The serializer of claim 1 wherein the shift registers send serial information over the communication bus to the slave provided on a different device than a device on which the bus matrix is provided.

4. The serializer of claim 1 wherein the shift registers receive serial information from the communication bus, the received serial information derived from information provided by the slave provided on a different device than a device on which the bus matrix is provided.

5. The serializer of claim 1 wherein the shift registers include an address signal shift register, a data signal shift register, and a control signal shift register.

6. The serializer of claim 2 wherein the finite state machine resynchronizes information provided based on a serial clock during serial transmission, to a clock governing the operation of the bus matrix.

7. The serializer of claim 6 wherein the shift registers each include a plurality of flip-flops and multiplexers, and a buffer on each tap of the shift register.

8. The serializer of claim 1 wherein a second serializer is coupled to the other end of the communication bus, the second serializer deserializing the information sent on the communication bus by the shift registers and serializing the information received on the communication bus by the shift registers.

9. The serializer of claim 1 wherein the bus matrix is an AHB matrix which uses the AMBA bus protocol.

10. A method for interfacing bus communications for a slave in a bus system, the method comprising:

receiving parallel bus information from a bus matrix, the parallel bus information addressed to the slave;

serializing the parallel bus information and sending the serial information on a communication bus; and

inserting a wait cycle to the bus matrix during the serialization of the parallel bus information and sending of serial information.

11. The method of claim 10 further comprising:

waiting for an indication that a response is being sent over the communication bus from the addressed slave; and

receiving and deserializing the response to provide the response to the bus matrix, wherein the wait cycle to the bus matrix extends until the response is ready to provide to the bus matrix.

12. The method of claim 10 wherein the receiving parallel bus information and inserting a wait cycle are performed by a finite state machine, and the serializing and deserializing of information is performed using one or more shift registers.

13. The method of claim 10 wherein the serial information is sent over the communication bus to the slave, the slave being provided on a different device than a device on which the bus matrix is provided.

14. The method of claim 10 wherein the received serial information from the communication bus is derived from information provided by the slave, the slave being provided on a different device than a device on which the bus matrix is provided.

15. The method of claim 10 further comprising resynchronizing the received serial information from a serial clock provided during serial transmission, to a clock governing the operation of the bus matrix.

16. The method of claim 10 wherein the bus matrix and slave are an AHB bus matrix and an AHB slave which use the AMBA bus protocol.

17. A method for interfacing bus communications for a slave in a bus system, the method comprising:

receiving serial information on a communication bus, the serial information derived from information provided by a bus matrix and addressed to a slave, the information provided by the bus matrix being derived from information from a master;

deserializing the serial information to obtain parallel information and providing the parallel information to the slave; and

receiving and serializing a response to the parallel information from the slave to provide the response on the communication bus to the bus matrix.

18. The method of claim 17 wherein the receiving of serial information includes receiving address information, data information, and control information from the bus matrix.

19. The method of claim 17 wherein the providing parallel information to the slave is performed by a finite state machine, and the deserializing and serializing of information is performed using one or more shift registers.

20. The method of claim 17 wherein the bus matrix is provided on a different device than a device on which the slave is provided.

21. The method of claim 17 wherein the received serial information from the communication bus is provided by a serializer provided on a different device than a device on which the slave is provided.

22. The method of claim 17 further comprising resynchronizing the received serial information from a serial clock provided during serial transmission, to a clock governing the operation of the slave.

23. The method of claim 17 wherein the bus matrix and slave are an AHB matrix and AHB slave which use the AMBA bus protocol.

24. A system including bus communication to a slave, the system comprising:

a bus matrix operative to communicate information using buses of the system, wherein the bus matrix is provided on a first device;

a first serializer coupled to the bus matrix and provided on a first device, the first serializer operative to serialize the information received from the bus matrix and send the serialized information over a communication bus;

a second serializer provided on a second device and coupled to the communication bus, the second serializer operative to receive the serialized information and deserialize the serialized information; and

a slave provided on the second device and coupled to the second serializer, the slave operative to provide a response to the information from the bus matrix, wherein the deserialized information is provided to the slave.

25. The system of claim 24 wherein the first device is a first integrated circuit chip and the second device is a second integrated circuit chip.

26. The system of claim 24 wherein the first and second serializers each include a finite state machine operative to introduce automatic wait cycles in the bus matrix to allow the serialization of the information.

27. A computer readable medium including program instructions to be implemented by a computer and for interfacing bus communications for a slave in a bus system, the program instructions for:

receiving parallel bus information from a bus matrix, the parallel bus information addressed to the slave;

serializing the parallel bus information and sending the serial information on a communication bus; and

inserting a wait cycle to the bus matrix during the serialization of the parallel bus information and sending of serial information.

28. A computer readable medium including program instructions to be implemented by a computer and for interfacing bus communications for a slave in a bus system, the program instructions for:

receiving serial information on a communication bus, the serial information derived from information provided by a bus matrix and addressed to a slave, the information provided by the bus matrix being derived from information from a master;

deserializing the serial information to obtain parallel information and providing the parallel information to the slave; and

receiving and serializing a response to the parallel information from the slave to provide the response on the communication bus to the bus matrix.