Flash micro-controller with shadow boot-loader SRAM for dual-device booting of micro-controller and host

• US 7,761,653 B2
• Filed: 10/19/2007
• Issued: 07/20/2010
• Est. Priority Date: 08/04/1999
• Status: Expired due to Fees

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Ma, Abraham C., Lee, Charles C., Chow, David Q., Yu, Frank
• Primary Examiner(s): Peugh; Brian R
• Application Number:
  US11/875,648
• Publication Number:
  US 20080040598A1
• Time in Patent Office: 1,005 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 9/441 Multiboot arrangements, i.e. selecting an operating system to be loaded

Abstract

A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The boot code includes an initial boot loader, boot code and a control program that are executed by the flash microcontroller, and an operating system OS image and an external-host control program that are executed by an external host. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A first-reset-read address from the external host is captured by the microcontroller during its boot sequence and stored in a mapping table along with a physical address of the block in the SRAM buffer with the operating system OS image and the external-host control program. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory.

Claims

1. A dual-booting flash microcontroller comprising:

a flash bus for connecting to a flash-memory chip, the flash bus carrying address, data, and commands to the flash-memory chip;

microcontroller boot code stored in the flash-memory chip in a first block;

host boot code stored in the flash-memory chip in a host-boot block;

a static random-access memory (SRAM) buffer;

a central processing unit (CPU) for executing instructions read from the SRAM buffer;

a host interface for connecting to an external host over a host bus;

a flash-memory interface for generating flash-control signals and for buffering commands, addresses, and data to the flash bus, and for reading and writing the SRAM buffer;

a boot-loader state machine, activated by a reset signal, for activating the flash-memory interface to read the microcontroller boot code from the flash-memory chip, the boot-loader state machine writing the microcontroller boot code to the first block in the SRAM buffer;

a mapping table storing mapping entries each having a logical address from the external host and a physical address of corresponding data stored in the flash-memory chip; and

an initial mapping entry storing a first-reset-read address generated by the external host while the microcontroller boot code is being executed by the CPU;

wherein the microcontroller boot code executed by the CPU activates the host interface to send the host boot code to the external host,

whereby the initial mapping entry is generated from the first-reset-read address during booting of the dual-booting flash microcontroller.

2. The dual-booting flash microcontroller of claim 1 further comprising:

flash parameter registers for storing flash parameters indicating access timing and structure of the flash-memory chip;

wherein the boot-loader state machine reads a flash identifier from the flash-memory chip to generate the flash parameters.

3. The dual-booting flash microcontroller of claim 2 further comprising:

a flash-reset generator, activated by the boot-loader state machine, the flash-reset generator generating a flash reset command applied to the flash-memory chip.

4. The dual-booting flash microcontroller of claim 2 wherein the host interface further comprises:

a clocked-data interface to the host bus that connects to the external host;

a bus transceiver for detecting and processing commands sent over the host bus;

a buffer for storing data sent over the host bus.

5. The dual-booting flash microcontroller of claim 1 further comprising:

a checksum generator that generates a final running checksum from bytes read from the SRAM buffer; and

an error detector, coupled to the checksum generator, for signaling an error when the final running checksum has an error value.

6. The dual-booting flash microcontroller of claim 5 further comprising:

a cache in the SRAM buffer, the cache having tags and data for caching data stored in the flash-memory chip.

7. A method for dual-booting a flash microcontroller and an external host comprising:

applying power to the flash microcontroller that has a static random-access memory (SRAM) buffer and a central processing unit (CPU);

activating a state machine on the flash microcontroller to read an initial boot loader from a first page in a first block of a flash memory coupled to the flash microcontroller by a flash bus;

using the state machine to write the initial boot loader to the SRAM buffer in the flash microcontroller;

resetting the CPU, causing the CPU to fetch instructions of the initial boot loader stored in the SRAM buffer;

executing on the CPU the initial boot loader by fetching instructions in the initial boot loader from the SRAM buffer;

reading a next page from the flash memory after the first page and writing the next page to a buffer area of the SRAM buffer as the initial boot loader is executed;

continuing to read next pages from the flash memory and copy the next pages to the SRAM buffer as the initial boot loader is executed until all pages of an extended boot code have been copied to the SRAM;

transferring execution from the initial boot loader to the extended boot code in the SRAM buffer;

executing on the CPU the extended boot code and a control program in the extended boot code by fetching instructions in the extended boot code from the SRAM buffer;

reading a host-boot block from the flash memory after the extended boot code and writing the host-boot block to the SRAM buffer as the extended boot code is executed until an external-host control program has been copied to the host-boot block in the SRAM buffer;

transferring execution from the control program in the extended boot code to the external-host control program by executing a last instruction in the extended boot code that causes the flash microcontroller to send a ready signal to the external host; and

sending the external-host control program read from the host-boot block in the SRAM buffer to the external host and executing the external-host control program on the external host to reboot the external host,

whereby the flash microcontroller is booted by fetching and executing instructions from the SRAM buffer and the external host is booted by fetching and executing instructions from host-boot block in the SRAM buffer.

8. The method for dual-booting of claim 7 further comprising:

receiving a first-reset address from the external host while the CPU in the flash microcontroller is executing boot code; and

creating a first entry in a mapping table, the first entry storing the first-reset address as a logical address, and storing an address of the host-boot block in the SRAM buffer as a physical address for the first entry,

whereby the first entry for the host-boot block is automatically generated during booting.

9. The method for dual-booting of claim 7 further comprising:

generating a running checksum as boot code is read from the flash memory into the SRAM buffer;

generating a final running checksum as a stored checksum at an end of the boot code is read from the flash memory; and

generating an error when the final running checksum is non-zero.

10. The method for dual-booting of claim 9 further comprising:

reading a backup copy of the boot code from the flash memory when the final running checksum is non-zero.

11. The method for dual-booting of claim 7 further comprising:

sending a flash-reset command to the flash memory when the state machine is executing;

reading a flash identifier from the flash memory after the flash-reset command is sent;

using the flash identifier to generate flash parameters; and

writing the flash parameters to flash parameter registers in the flash microcontroller.

12. The method for dual-booting of claim 11 further comprising:

upgrading boot code stored in the flash memory by;

locating an older copy of the boot code stored in an upgrading block in the flash memory;

erasing the older copy in the flash memory; and

writing an upgraded copy of the boot code to the upgrading block.

13. The method for dual-booting of claim 12 further comprising:

verifying the upgraded copy by reading the upgraded copy of the boot code from the upgrading block to generate a final running checksum; and

repeating erase and writing of the upgrading block when the final running checksum is non-zero.

14. A dual-device booting flash microcontroller comprising:

external host interface means for connecting to an external host;

flash bus means for connecting to a flash memory, the flash bus means carrying address, data, and commands to the flash memory;

flash-memory controller means for generating flash-control signals and for buffering commands, addresses, and data to the flash bus means;

volatile buffer means for storing instructions in a volatile memory;

external-host boot sequence means, stored in the flash memory, for transfer to the external host over the external host interface means, wherein the external-host boot sequence means contains instructions for execution by the external host after the external host is re-booted;

processor means for fetching and executing instructions from the volatile buffer means;

extended-local boot sequence means, stored in the flash memory, for instructing the processor means to read the external-host boot sequence means from the flash memory and to write the external-host boot sequence means into the volatile buffer means;

initial boot loader means, stored in the flash memory, for instructing the processor means to read the extended-local boot sequence means from the flash memory and to write the extended-local boot sequence means into the volatile buffer means; and

hardwired initializer means, activated by a reset signal, for activating the flash-memory controller means to read the initial boot loader means from the flash memory, and for writing the initial boot loader means as first instructions to the volatile buffer means.

15. The dual-device booting flash microcontroller of claim 14 further comprising:

flash parameter register means for storing flash parameters indicating timing and access specifications of the flash memory; and

parameter write means, activated by the hardwired initializer means, for reading a flash identifier from the flash memory, for using the flash identifier to generate flash parameters, and for writing the flash parameters to the flash parameter register means;

wherein the flash-memory controller means reads the flash parameters from the flash parameter register means to generate flash-control signals that meet the timing and access specifications of the flash memory,

whereby flash parameters are extracted during initialization.

16. The dual-device booting flash microcontroller of claim 14 further comprising:

checksum means for generating a running checksum when boot code is read from the flash memory, wherein the boot code comprises the external-host boot sequence means or the extended-local boot sequence means;

verify means for comparing the running checksum after the boot code has been read from the flash memory to a valid checksum value, and for signaling an error when the valid checksum value is not generated by the checksum means; and

address means, activated by the error signaled by the verify means, for switching an address to point to an alternate copy of the boot code in the flash memory.

17. The dual-device booting flash microcontroller of claim 14 wherein the initial boot loader means further comprises:

an initial jump instruction that is executed before other instructions in the initial boot loader means, the initial jump instruction causing the processor means to fetch subsequent instructions in the initial boot loader means from a jump target address in the volatile buffer means.

18. The dual-device booting flash microcontroller of claim 14 further comprising:

reset means for resetting the processor means to begin fetching and executing instructions from the initial boot loader means stored in the volatile buffer means, the reset means activating the processor means in response to the hardwired initializer means.

19. The dual-device booting flash microcontroller of claim 14 further comprising:

mapping table means for storing mapping entries that associate a logical address from the external host with a physical address in the flash memory or in the volatile buffer means;

first read reset means for receiving a first read reset address from the external host and for storing the first read reset address as the logical address in a first entry in the mapping table means; and

matching means for writing an address of the external-host boot sequence means stored in the volatile buffer means as the physical address for the first entry in the mapping table means,

whereby the first entry is generated automatically from the first read reset address.

20. The dual-device booting flash microcontroller of claim 19 further comprising:

external ready means, activated when the external-host boot sequence means has been loaded into the volatile buffer means, for activating the external host to re-boot and fetch and execute instructions from the external-host boot sequence means stored in the volatile buffer means,

whereby the external host is also re-booted.