Memory device with data security in a processor
First Claim
1. An integrated circuit, comprising:
- a processor;
a plurality of interfaces that provide external access to the integrated circuit, the plurality of interfaces comprising a USB interface, a JTAG interface and a parallel interface; and
a non-volatile memory device partitioned into a plurality of memory portions including a first memory portion and a second memory portion, where the first memory portion includes initialization executable program instructions that are executed upon power-up of the integrated circuit, and where the second memory portion includes (i) a first password, (ii) a second password, (iii) program control register data associated with enabling or disabling of the plurality of interfaces, and (iv) executable program instructions for encrypting or decrypting data, where the first and second passwords are associated with access by a user to the executable program instructions;
where bit locations of the program control register data associated with the plurality of interfaces are hardwired within the integrated circuit with interface control circuitry, such that upon a reset of the processor the bit locations of the program control register data are read by the interface control circuitry to determine which of the plurality of interfaces should be enabled based upon uniquely associated control bits in the program control register data.
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Accused Products
Abstract
A memory device containing data to be protected is integrated with a microprocessor and includes a first and a second memory portion with different accessibilities. The integration of the memory device on the same integrated circuit (IC) or chip as the microprocessor permits a combination of protective hardware and software measures that are not possible with a memory device that is on a different IC than the microprocessor. The first memory portion holds an initialization program that also serves as a boot program during decryption, and the second memory portion holds a user program, for example, a program for decrypting and/or decoding received data. Such data may be, for example, audio data encoded according to the MP3 standard and encrypted with a secret or public password against unauthorized reception.
46 Citations
16 Claims
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1. An integrated circuit, comprising:
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a processor; a plurality of interfaces that provide external access to the integrated circuit, the plurality of interfaces comprising a USB interface, a JTAG interface and a parallel interface; and a non-volatile memory device partitioned into a plurality of memory portions including a first memory portion and a second memory portion, where the first memory portion includes initialization executable program instructions that are executed upon power-up of the integrated circuit, and where the second memory portion includes (i) a first password, (ii) a second password, (iii) program control register data associated with enabling or disabling of the plurality of interfaces, and (iv) executable program instructions for encrypting or decrypting data, where the first and second passwords are associated with access by a user to the executable program instructions; where bit locations of the program control register data associated with the plurality of interfaces are hardwired within the integrated circuit with interface control circuitry, such that upon a reset of the processor the bit locations of the program control register data are read by the interface control circuitry to determine which of the plurality of interfaces should be enabled based upon uniquely associated control bits in the program control register data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit, comprising:
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a processor; a plurality of interfaces that provide external access to the integrated circuit; and a non-volatile memory device partitioned into a plurality of memory portions including a first memory portion and a second memory portion, where the first memory portion includes initialization executable program instructions that are executed upon power-up of the integrated circuit, and where the second memory portion includes (i) a first password, (ii) a second password, (iii) program control register data associated with enabling or disabling of the plurality of interfaces and (iv) executable program instructions for encrypting or decrypting data, where the first and second passwords are associated with access by a user to the executable program instructions; where bit locations of the program control register data associated with the plurality of interfaces are hardwired within the integrated circuit with interface control circuitry, such that upon a reset of the processor the bit locations of the program control register data are input to the interface control circuitry to determine which of the plurality of interfaces should be enabled based upon uniquely associated control bits in the program control register data. - View Dependent Claims (13, 14, 15)
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16. An integrated circuit, comprising:
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a processor; a plurality of interfaces in communication with the processor, the plurality of interfaces providing external access to the integrated circuit; and a non-volatile memory partitioned into a plurality of memory portions including a first memory portion and a second memory portion, the first memory portion including initialization executable program instructions executable upon power-up of the integrated circuit, the second memory portion including a first password; a second password, where each of the first and the second passwords have a first type of access and are associated with user access to the executable program instructions; program control register data associated with enabling or disabling of the plurality of interfaces; and executable program instructions associated with encrypting or decrypting data; where bit locations of the program control register data associated with the plurality of interfaces are hardwired within the integrated circuit with interface control circuitry, such that upon a reset of the processor the bit locations of the program control register data are read by the interface control circuitry to determine which of the plurality of interfaces should be enabled based upon uniquely associated control bits in the program control register data.
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Specification