Method, apparatus, and system for protecting memory

• US 7,761,780 B2
• Filed: 11/22/2006
• Issued: 07/20/2010
• Est. Priority Date: 11/28/2005
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kanai, Tatsunori
• Primary Examiner(s): Baker; Stephen M
• Application Number:
  US11/603,037
• Publication Number:
  US 20070124557A1
• Time in Patent Office: 1,336 Days
• Field of Search: 714/805, 711/164
• US Class Current: 714/805
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

A parity adder obtains a second data by adding a parity for first data to be written to a memory to the first data. An access-key register holds an access key unique to a source of request. A first operating unit obtains a third data by calculating an XOR between the second data and the access key, the access key being set by the source of request for writing data to the memory. A second operating unit obtains a fourth data by calculating an XOR between the access key and the third data. A syndrome calculator calculates a syndrome from the third data, the access key being set by the source of request for reading data from the memory. A determining unit determines whether to output the third data as the first data, based on calculated syndrome.

Claims

1. An apparatus for protecting a memory, comprising:

a parity generator that generates a parity of first data to be written to the memory;

a parity adder that obtains a second data by adding the parity to the first data;

an access-key register that holds an access key unique to a source of request for writing data to the memory or for reading data from the memory, the access key being set by the source of request and being used for accessing the memory;

a first operating unit that obtains a third data by calculating an XOR between the second data and the access key, the access key being set in the access-key register by the source of request for writing data to the memory;

a writing unit that writes the third data to the memory;

a second operating unit that obtains a fourth data by calculating an XOR between the access key and the third data, the access key being set in the access-key register by the source of request for reading data from the memory;

a syndrome calculator that calculates a syndrome from the third data; and

a determining unit that determines whether to output the third data as the first data, based on calculated syndrome.

2. The apparatus according to claim 1, further comprising:

a write-access-key table that stores a memory address area of the memory in association with the access key; and

a write permitting unit that permits a write of the third data to the memory address area associated with the access key set by the source of request in the write-access-key table, wherein

the writing unit writes the third data to the memory address area to which the writing of the third data is permitted.

3. The apparatus according to claim 1, further comprising:

a read-access-key table that stores a memory address of the memory in association with the access key; and

a key selecting unit that, upon receiving a designation of the memory address from the source of request, selects the access key associated with designated memory address from the read-access-key table, wherein

the access-key register holds selected access key.

4. The apparatus according to claim 1, further comprising:

a data editing unit that generates data-representing a single-bit data to be written to the memory by an XOR of four bits of data, locating each of the four bits in different words, locating a first bit and a second bit in a first bit location, locating a third bit and a fourth bit in a second bit location, respectively locating zero and one in the second bit location of the words that include the first bit and the second bit, and respectively locating zero and one in the first bit location of the words that include the third bit and the fourth bit, wherein

the parity generator generates the parity for each of the words obtained by the data editing unit.

5. The apparatus according to claim 1, wherein

the second operating unit performs the XOR operation of the access key and the third data, upon acquiring a request for writing the first data from the source of request, and

the parity generator generates the parity for the first data when the determining unit determines to output the third data as the first data based on the calculated syndrome.

6. The apparatus according to claim 1, wherein

the source of request is either one of a processor and a process.

7. The apparatus according to claim 1, further comprising:

an acquiring unit that acquires an instruction to generate the access key from the source of request;

a key generator that generates the access key unique to the source of request upon acquiring the instruction; and

a key transmitting unit that transmits generated access key to the source of request.

8. The apparatus according to claim 7, wherein

the key generator generates the access key for each of a plurality of words corresponding to a unit of accessing the memory by the source of request.

9. The apparatus according to claim 7, wherein

the key generator generates the access key that satisfies a condition that is syndrome detected as double errors even when the syndrome is calculated from an XOR between the second data, an access key to be generated, and any one of existing access keys.

10. The apparatus according to claim 9, wherein

the key generator generates the access key so that a Hamming distance between the access key to be generated and any one of the existing access keys is equal to or more than four.

11. A system for protecting a memory, the system comprising:

a processor;

a memory controller; and

a memory protecting apparatus that protects an external memory, wherein

the memory protecting apparatus includes

a parity generator that generates a parity of first data to be written to the memory;

a parity adder that obtains a second data by adding the parity to the first data;

an access-key register that holds an access key unique to a source of request for writing data to the memory, the access key being set by the source of request and being used for accessing the memory or for reading data from the memory;

a first operating unit that obtains a third data by calculating an XOR between the second data and the access key, the access key being set in the access-key register by the source of request for writing data to the memory;

a writing unit that writes the third data to the memory;

a second operating unit that obtains a fourth data by calculating an XOR between the access key and the third data, the access key being set in the access-key register by a source of request for reading data from the memory;

a syndrome calculator that calculates a syndrome from the third data; and

a determining unit that determines whether to output the third data as the first data, based on calculated syndrome.

12. A system for protecting a memory, the system comprising:

a memory controller; and

a memory protecting apparatus that protects an external memory, wherein

the memory protecting apparatus includes

a parity generator that generates a parity of first data to be written to the memory;

a parity adder that obtains a second data by adding the parity to the first data;

an access-key register that holds an access key unique to a source of request for writing data to the memory or for reading data from the memory, the access key being set by the source of request and being used for accessing the memory;

a first operating unit that obtains a third data by calculating an XOR between the second data and the access key, the access key being set in the access-key register by the source of request for writing data to the memory;

a writing unit that writes the third data to the memory;

a second operating unit that obtains a fourth data by calculating an XOR between the access key and the third data, the access key being set in the access-key register by a source of request for reading data from the memory;

a syndrome calculator that calculates a syndrome from the third data; and

a determining unit that determines whether to output the third data as the first data, based on calculated syndrome.

13. A system for protecting a memory, the system comprising:

a memory; and

a memory protecting apparatus that protects the memory, wherein

the memory protecting apparatus includes

a parity generator that generates a parity of first data to be written to the memory;

a parity adder that obtains a second data by adding the parity to the first data;

an access-key register that holds an access key unique to a source of request for writing data to the memory or for reading data from the memory, the access key being set by the source of request and being used for accessing the memory;

a first operating unit that obtains a third data by calculating an XOR between the second data and the access key, the access key being set in the access-key register by the source of request for writing data to the memory;

a writing unit that writes the third data to the memory;

a second operating unit that obtains a fourth data by calculating an XOR between the access key and the third data, the access key being set in the access-key register by a source of request for reading data from the memory;

a syndrome calculator that calculates a syndrome from the third data; and

a determining unit that determines whether to output the third data as the first data, based on calculated syndrome.

14. A method of protecting a memory, the method comprising:

generating a parity of first data to be written to the memory;

obtaining a second data by adding the parity to the first data;

setting an access key unique to a source of request for writing data to the memory or for reading data from the memory in an access-key register, the access key being set by the source of request and being used for accessing the memory;

obtaining a third data by calculating an XOR between the second data and the access key, the access key being set in the access-key register by the source of request for writing data to the memory;

writing the third data to the memory;

obtaining a fourth data by calculating an XOR between the access key and the third data, the access key being set in the access-key register by the source of request for reading data from the memory;

calculating a syndrome from the third data; and

determining whether to output the third data as the first data, based on calculated syndrome.

15. The method according to claim 14, further comprising:

acquiring an instruction to generate the access key from the source of request;

generating the access key unique to the source of request upon acquiring the instruction; and

transmitting generated access key to the source of request.

16. The method according to claim 14, further comprising:

permitting a write of the third data to a memory address area associated with the access key set by the source of request in a write-access-key table that stores the memory address area of the memory in association with the access key; and

the third data to the memory address area to which the writing of the third data is permitted.

17. The method according to claim 14, further comprising:

selecting unit that, upon receiving a designation of a memory address from the source of request, the access key associated with designated memory address from a read-access-key table that stores the memory address of the memory in association with the access key; and

holding selected access key.

18. The method according to claim 14, further comprising:

generating data representing a single-bit data to be written to the memory by an XOR of four bits of data, locating each of the four bits in different words, locating a first bit and a second bit in a first bit location, locating a third bit and a fourth bit in a second bit location, respectively locating zero and one in the second bit location of the words that include the first bit and the second bit, and respectively locating zero and one in the first bit location of the words that include the third bit and the fourth bit; and

generating the parity for each of generated words.

19. The method according to claim 14, further comprising:

performing the XOR operation of the access key and the third data, upon acquiring a request for writing the first data from the source of request; and

generating the parity for the first data when the determining unit determines to output the third data as the first data based on the calculated syndrome.

20. The method according to claim 14, wherein

the source of request is either one of a processor and a process.