Method, apparatus and article to load new instructions on processor based devices, for example, automatic data collection devices

• US 7,761,864 B2
• Filed: 08/09/2005
• Issued: 07/20/2010
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Original Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Inventors: Millican, Art, White, Allen S., Dale, Joel
• Primary Examiner(s): Zhen; Wei Y
• Assistant Examiner(s): Nahar; Qamrun
• Application Number:
  US11/200,503
• Publication Number:
  US 20070038990A1
• Time in Patent Office: 1,806 Days
• Field of Search: 717168-173, 713/1, 713/2, 713/100
• US Class Current: 717/168
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

Methods, apparatus and articles facilitate the loading of a set of new instructions to replace set of existing instructions on a processor based device, for example an automatic data collection device. For example, a new operating system may replace an existing operating system using an executable that disables interrupts and/or exceptions. The new operating system may execute with, or without booting. The set of new instructions may be fragmented to fit the block size of a nonvolatile programmable memory, and/or may be compressed. Validation values such as check sums and/or error correction may be employed.

Claims

1. A method of loading new instructions on target devices, the method comprising:

receiving a new instruction loading executable at a target device during a first period of time;

executing the new instruction loading executable on a processor of the target device during a second period of time subsequent to the first period of time, and wherein for a time span extending from a start of the first period of time to a start of the second period of time, the processor of the target device is not booted;

receiving at least a portion of a set of new instructions at the target device;

disabling an interrupt function at the target device based on executing the new instruction loading executable;

erasing a first block of a nonvolatile programmable memory of the target device; and

loading at least a first portion of the set of new instructions to the erased first block of the nonvolatile programmable memory on the target device based on the execution of the new instruction loading executable.

2. The method of claim 1, further comprising

executing an existing operating system of the target device stored in a nonvolatile programmable memory of the target device on a processor of the target device during the first period of time, and wherein disabling an interrupt function at the target device based on executing the new instruction loading executable includes suspending execution of the existing operating system of the target device based on executing the new instruction loading executable.

3. The method of claim 2 wherein the set of new instructions comprises a new operating system, wherein the first block of the nonvolatile programmable memory of the target device stored a first portion of the existing operating system prior to erasure of the first block of the nonvolatile programmable memory, wherein the first portion of the set of new instructions loaded into the first block of the nonvolatile programmable memory comprises a first portion of the new operating system, further comprising:

subsequent to loading at least the first portion of the set of new instructions to the erased first block of the nonvolatile programmable memory on the target device, erasing a second block of the nonvolatile programmable memory of the target device having a second portion of the existing operating stored therein; and

prior to erasing a third block of the nonvolatile memory, loading at least a second portion of the new operating system to the erased second block of the nonvolatile programmable memory on the target device, wherein the nonvolatile memory comprises at least three blocks of equal size.

4. The method of claim 3 wherein receiving at least a portion of a set of new instructions at the target device comprises receiving the set of new instructions in at least two compressed fragments, each of the fragments sized to fit a block size of any block of the nonvolatile programmable memory when uncompressed.

5. The method of claim 4, further comprising:

uncompressing at least a first one of the fragments before the first portion of the new operating system is loaded into to the erased first block of the nonvolatile programmable memory on the target device.

6. The method of claim 5, further comprising:

verifying at least the uncompressed first one of the fragments before the first portion of the new operating system is loaded into to the erased first block of the nonvolatile programmable memory on the target device.

7. The method of claim 3, wherein the target device includes a volatile memory and the processor is communicatively coupled to the nonvolatile programmable memory and the volatile memory, wherein receiving at least a portion of a set of new instructions at the target device includes storing the at least portion of the set of new instructions in the volatile memory, and wherein while the existing operating system is executed and while the existing operating system is suspended, the volatile memory on the target device does not store a copy of the existing operating system.

8. The method of claim 7, further comprising:

executing at least a portion of the new operating system without booting the processor on the target device after a last portion of the set of new instructions has been loaded to a respective block of the nonvolatile programmable memory of the target device.

9. The method of claim 5 wherein receiving at least a portion of a set of new instructions at the target device comprises receiving the set of new instructions in a file system of the target device, the method further comprising:

copying at least the uncompressed first one of the fragments to a respective area of a volatile memory of the target device before the first portion of the new operating system is loaded into to the erased first block of the nonvolatile programmable memory on the target device.

10. The method of claim 1 wherein receiving at least a portion of a set of new instructions at the target device comprises receiving the set of new instructions in at least two fragments.

11. The method of claim 1 wherein receiving at least a portion of a set of new instructions at the target device comprises receiving the set of new instructions in at least two compressed fragments.

12. The method of claim 1, further comprising:

requesting the set of new instructions from a host device.

13. The method of claim 1, further comprising:

cold booting the processor on the target device after a last portion of the set of new instructions has been loaded to a respective block of the nonvolatile programmable memory of the target device, wherein the last portion of the set of new instructions is loaded to the respective block of the nonvolatile programmable memory after the start of the second period of time.

14. The method of claim 1 wherein the at least a portion of a set of new instructions is received at the target device before executing the new instruction loading executable on the target device.

15. A method of loading new instructions on a target device, the method comprising:

providing a new instruction loading executable that includes a new instruction disable interrupt executable having at least one instruction to disable a respective interrupt function of a processor of a target device to the target device, wherein an existing operating system stored in a nonvolatile programmable memory and executed by the processor of the target device is suspended in response to the processor of the target device executing the least one instruction to disable a respective interrupt function of the processor of the target device; and

providing a set of new instructions comprising the new operating system at the target device in at least three fragments, each respective fragment of the at least three fragments having a respective uncompressed size selected to fit into a respective block of the nonvolatile programmable memory of the target device, wherein the nonvolatile programmable memory of the target device is comprised of at least three blocks of equal size, and wherein each respective fragment is loaded into a respective block of the nonvolatile programmable memory of the target device.

16. The method of claim 15, further comprising:

determining the set of new instructions for the target device based at least in part on a characteristic of the target device.

17. The method of claim 15 wherein providing a set of new instructions at the target device in at least three fragments comprises providing the set of new instructions to the target device in at least three compressed fragments.

18. The method of claim 15 wherein providing a set of new instructions at the target device in at least two fragments is executed in response to a request generated by the new instruction loading executable executing on the target device.

19. A computing device, comprising:

a nonvolatile programmable memory comprising a plurality of blocks having an existing operating system stored therein;

a volatile memory capable of storing instructions and not having the existing operating system stored therein;

a processor operable to execute instructions stored in at least one of the volatile memory and the nonvolatile programmable memory;

wherein the nonvolatile programmable memory stores a new instruction loading executable that causes the processor to load a set of new instructions on the computing device, by;

disabling an interrupt function of the processor; and

concurrently while the interrupt function is disabled and while the volatile memory does not have the existing operating stored therein, and for at least three times, sequentially,

erasing a respective block of the nonvolatile programmable memory of the computing device, and

loading a respective portion of the set of new instructions to the respective erased block of the nonvolatile programmable memory on the computing device, and wherein the processor sequentially erases a respective block of the nonvolatile programmable memory and then loads a respective portion of the set of new instructions to the most currently erased respective block of the nonvolatile programmable memory prior to erasing a subsequent block of the of the nonvolatile programmable memory of the computing device.

20. The computing device of claim 19, wherein the new instruction loading executable includes a new instruction disable interrupt executable having at least one instruction to disable a respective interrupt function of the processor of the computing device, and wherein disabling an interrupt function of the processor includes suspending execution of the existing operating system of the computing device based on the processor executing the new instruction loading executable.

21. The computing device of claim 20 wherein the set of new instructions comprises a new operating system, wherein erasing a respective block of the nonvolatile programmable memory of the computing device includes erasing a respective portion of the existing operating system of the computing device, and wherein loading a respective portion of the set of new instructions to the respective erased block of the nonvolatile programmable memory on the computing device includes loading a respective portion of the new operating system to the respective erased block of the nonvolatile programmable memory on the computing device.

22. The computing device of claim 21 wherein the new instruction loading executable causes the processor to execute at least a portion of the new operating system without booting the computing device.

23. The computing device of claim 20 wherein the processor loads the set of new instructions on the computing device, by:

decompressing fragments of the set of new instructions before loading the portions of the set of new instructions to respective ones of the erased blocks of the nonvolatile programmable memory of the computing device.

24. The computing device of claim 23 wherein the processor loads the set of new instructions on the computing device, by:

storing the fragments in an operating space of the volatile memory of the computing device before decompressing fragments of the set of new instructions.

25. The computing device of claim 20 wherein the new instruction loading executable causes the processor to load the set of new instructions on the computing device further by:

cold booting the computing device after all of the portions of the set of new instructions have been loaded to the respective ones of the blocks of the nonvolatile programmable memory of the computing device.

26. A system for loading new instructions on target devices, the system comprising:

at least one memory storing at least one new instruction loading executable and at least one set of new instructions for loading onto target devices, the at least one new instruction loading executable includes a new instruction disable interrupt executable having at least one instruction to disable a respective interrupt function of a respective processor of a respective target device;

at least one communications port coupleable to provide communications with target devices; and

a processor operable to provide the set of new instructions in at least three fragments, each respective fragment of the at least three fragments having a respective uncompressed size selected to fit into a respective block of a nonvolatile programmable memory of an identified target device, wherein the nonvolatile programmable memory of the target device is comprised of at least three blocks of equal size.

27. The system of claim 26 wherein the processor is further operable to select the set of new instructions from a plurality of sets of new instructions, where each set of new instructions is previously divided into fragments of different sizes.

28. The system of claim 26 wherein the processor is further operable to divide the set of new instructions into fragments of a size that is based on a block size of the nonvolatile programmable memory of the identified target device.

29. A computer-readable recordable medium storing instructions for causing a processor of a computing device to facilitate loading new instructions on the computing device by:

disabling an interrupt function of the processor of the computing device; and

for at least three blocks of a flash memory of the computing device and at least three portions of a set of new instructions, sequentially,

erasing a respective block of the flash memory of the computing device, and

loading a respective portion of the set of new instructions to the respective erased block of the flash memory on the computing device.

30. The computer-readable recordable medium of claim 29 wherein the instructions that cause the processor to facilitate loading new instructions on the computing device by disabling an interrupt function of the processor of the computing device includes instructions that cause the processor to facilitate loading new instructions on the computing device by suspending execution of an existing operating system by the processor, and wherein the portions of the set of new instructions are loaded to respective ones of the erased blocks of the flash memory on the computing device while the interrupt function of the processor of the computing device is disabled and the execution of the existing operating system is suspended.

31. The computer-readable recordable medium of claim 29 wherein the instructions cause the processor to facilitate loading new instructions on the computing device further by:

decompressing a number of fragments of the set of new instructions before loading the portions of the set of new instructions to respective ones of the erased blocks of the flash memory on the computing device.

32. The computer-readable recordable medium of claim 31 wherein the instructions cause the processor to facilitate loading new instructions on the computing device further by:

storing the fragments in an operating space of a volatile memory of the computing device before decompressing fragments of the set of new instructions.

33. The computer-readable recordable medium of claim 31 wherein the instructions cause the processor to facilitate loading new instructions on the computing device further by:

cold booting the computing device after all of the portions of the set of new instructions have been loaded to the respective ones of the erased blocks of the flash memory of the computing device.

34. The computer-readable recordable medium of claim 29 wherein the set of new instructions comprises a new operating system and the computer-readable medium causes the processor to execute at least a portion of the new operating system without first booting the computing device.

35. A computer-readable recordable medium storing instructions for causing a computer to facilitate loading new instructions on target devices by:

providing a new instruction loading executable to a target device having a nonvolatile programmable memory with an existing operating system of the target device stored therein, a volatile memory, a processor, and at least one bus that communicatively couples the nonvolatile programmable memory, the volatile memory and processor, the new instruction loading executable being such that when executed the new instruction loading executable loads a new operating system into the nonvolatile memory of the target device while the existing operating system is not copied into the volatile memory; and

providing a set of new instructions at the target device in at least three fragments, each respective fragment of the at least three fragments having a respective uncompressed size selected to fit into a respective block of a flash memory of the target device, wherein the flash memory is comprised of at least three blocks of equal size, and wherein each respective fragment is loaded into a respective block of the flash memory of the target device.

36. The computer-readable recordable medium of claim 35 wherein respective blocks of the flash memory are of equal block size, and wherein the instructions cause the computer to facilitate loading new instructions on target devices further by:

selecting the set of new instructions from a plurality of sets of new instructions based at least in part on the block size of the flash memory of the target device, where each set of new instructions is previously divided into fragments, the fragments of a first one of the plurality of sets of new instructions being of a different size than the fragments of a second one of the plurality of sets of new instructions.

37. The computer-readable recordable medium of claim 35 wherein the instructions cause the computer to facilitate loading new instructions on target devices further by:

dividing the set of new instructions into fragments of a size that is based on a block size of the flash memory of an identified target device.

43. The method of claim 37 wherein the new instruction loading executable is received during a first time period, and wherein executing the new instruction loading executable on the target device further comprises:

executing the new instruction loading executable on the target device during a second period of time subsequent to the first period of time, and wherein for a time span extending from a start of the first period of time to a start of the second period of time, a processor of the target device is not booted.

38. A method of loading new instructions on a target device having a nonvolatile memory, the method comprising:

executing an existing operation system of a target device with a processor of the target device, the target device including a nonvolatile programmable memory having the existing operating system stored therein, a volatile memory being free of the existing operating system while the existing operating system is executed by the processor, the processor communicatively coupled to the nonvolatile programmable memory and the volatile memory;

receiving a new instruction loading executable at the target device;

receiving a number (N) of fragments of a set of new instructions comprising a new operating system of the target device at the target device, where N is at least three;

executing the new instruction loading executable on the processor of the target device;

suspending execution of the existing operating system at the target device based at least on disablement of an interrupt function at the target device via execution of the new instruction loading executable; and

for N times sequentially,

erasing a respective block of the nonvolatile programmable memory of the target device that stores a respective portion of the existing operating system of the target device, and

loading a respective portion of the new operating system to a respective erased block of the nonvolatile programmable memory on the target device.

39. The method of claim 38, further comprising:

after erasing at least one block of the nonvolatile program memory and prior to erasing another block of the nonvolatile program memory,

determining whether to erase another block of the nonvolatile program memory.

40. The method of claim 39 wherein determining whether to erase another block of the nonvolatile program memory comprises determining whether all N fragments of the set of new instructions have been loaded into the nonvolatile program memory.

41. The method of claim 38, the method further comprising:

cold booting a processor on the target device after all of the fragments of the set of new instructions have been loaded to the respective ones of the erased blocks of the nonvolatile programmable memory.

42. The method of claim 38 wherein the set of new instructions comprises a new operating system cold booting a processor on the target device after all of the fragments of the set of new instructions have been loaded to the respective ones of the erased blocks of the nonvolatile programmable memory.