Method for forming isolation structure of different widths in semiconductor device

• US 7,763,524 B2
• Filed: 06/28/2007
• Issued: 07/27/2010
• Est. Priority Date: 10/31/2006
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Nam-Jae
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Fan; Michele
• Application Number:
  US11/823,774
• Publication Number:
  US 20080176379A1
• Time in Patent Office: 1,125 Days
• Field of Search: 438/400, 438/424, 438/427, 438/435, 257/E21.537, 257/E21.54, 257/E21.545, 257/E21.546, 257/E21.548
• US Class Current: 438/427
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for forming an isolation structure in a semiconductor device including a substrate having a first region and a second region, the second region having an isolation structure formed to a larger width than a plurality of isolation structures formed in the first region, is provided. The method includes etching portions of the first and second regions of the substrate to form first and second trenches, wherein a width of the second trench is larger than that of the first trench, forming a first insulation layer to fill a portion of the first and second trenches, forming a barrier layer to fill the first and second trenches, etching portions of the first insulation layer and the barrier layer in the first region, removing the barrier layer, and forming a second insulation layer over the first insulation layer.

Claims

1. A method for forming an isolation structure in a semiconductor device, wherein the semiconductor device includes a substrate comprising a first region and a second region, the second region having an isolation structure formed to a larger width than a plurality of isolation structures formed in the first region, the method comprising:

etching portions of the first and second regions of the substrate to form first and second trenches, respectively, wherein a width of the second trench is larger than that of the first trench;

forming a first insulation layer to fill a portion of the first and second trenches;

directly after forming the first insulation layer, forming a barrier layer over the first insulation layer;

etching portions of the first insulation layer and the barrier layer;

removing the barrier layer; and

forming a second insulation layer over the first insulation layer to fill the first and second trenches,

wherein the barrier layer is foamed to have a smaller thickness in the second region than in the first region,

wherein etching portions of the first insulation layer and the barrier layer in the first region comprises;

forming a photoresist pattern over the barrier layer of the second trench; and

performing a first etch process to etch the portions of the first insulation layer and the barrier layer in the first region using the photoresist pattern.

2. The method of claim 1, further comprising, after performing the first etch process, performing a second etch process to etch portions of the first insulation layer and the barrier layer using the photoresist pattern such that a portion of inner sidewalls of the first trenches is exposed.

3. The method of claim 2, wherein the second etch process is performed under a certain condition to etch the first insulation layer, wherein the second etch process comprises etching the barrier layer at a lower rate than the first insulation layer while the first insulation layer is etched.

4. The method of claim 2, wherein the first etch process comprises performing a dry etch process and the second etch process comprises performing a wet etch process.

5. The method of claim 1, wherein the barrier layer comprises a material having a different etch rate than the first insulation layer under substantially the same etch condition.

6. The method of claim 1, wherein the barrier layer comprises one of an inorganic-based anti-reflective coating layer and an organic-based anti-reflective coating layer.

7. The method of claim 1, wherein the first and second insulation layers comprise substantially the same material.

8. The method of claim 7, wherein the first and second insulation layers comprise a high density plasma (HDP) oxide layer.

9. The method of claim 1, wherein removing the barrier layer comprises performing a wet etch process.

10. The method of claim 1, wherein the first insulation layer has depressed portions above middle portions of the first and second trenches.

11. The method of claim 10, wherein the barrier layer substantially fills the depressed portions of the first insulation layer.

12. The method of claim 1, further comprising, after forming the first insulation layer, performing a curing process on the first insulation layer to densify a layer property of the first insulation layer.

13. The method of claim 1, further comprising, after forming the second insulation layer, performing a curing process on the second insulation layer to densify a layer property of the second insulation layer.

14. The method of claim 1, further comprising, prior to etching the portions of the first and second regions of the substrate to form the first and second trenches, forming a structure over the substrate to be patterned while etching the portions of the first and second regions of the substrate to form the first and second trenches.

15. The method of claim 14, wherein forming the structure comprises:

forming a gate insulation layer over the substrate;

forming a conductive layer for forming a gate electrode over the gate insulation layer; and

forming a padding layer over the conductive layer.

16. The method of claim 15, further comprising, after forming the second insulation layer, planarizing the second insulation layer to expose an upper portion of the structure.

17. The method of claim 15, wherein the padding layer comprises a nitride-based layer.

18. The method of claim 1, wherein the first region comprises a cell region and the second region comprises a peripheral region.