Peripheral circuits of three-dimensional mask-programmable memory

• US 7,763,911 B2
• Filed: 01/07/2005
• Issued: 07/27/2010
• Est. Priority Date: 04/08/2002
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Dang; Phuc T
• Assistant Examiner(s): Tran; Thanh Y
• Application Number:
  US11/031,637
• Publication Number:
  US 20050133875A1
• Time in Patent Office: 2,027 Days
• Field of Search: 257/211, 257/390, 257/67, 257/401, 257/300, 257/303, 257/306, 257/296, 257/E21.66, 257/E21.662, 257/E21.666, 257/E21.667, 257/E21.671, 257/E21.677, 257/E27.077, 257/E21.678, 257/686, 257/225, 438/155, 365/49.16, 365/49.1, 365/134
• US Class Current: 257/211
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/76 Unipolar devices , e.g. field effect transistors

Abstract

The present invention discloses several preferred mask-programmable 3-D memory (3D-MPROM) structures, including pillar-shaped 3D-MPROM, natural-junction 3D-MPROM, interleaved 3D-MPROM, and separate 3D-MPROM. The present invention also makes further improvements to its peripheral circuits. The use of sense-amplifier can significantly lower the leakage-current requirement on the 3D-ROM memory cell. Self-timing can improve the 3D-ROM speed and reduce its power consumption.

Claims

1. A three-dimensional mask-programmable read-only memory (3D-MPROM), comprising:

a semiconductor substrate comprising a plurality of transistor-based differential sense-amplifiers with first and second inputs;

a plurality of 3D-MPROM levels stacked above said semiconductor substrate, said 3D-MPROM levels comprising a plurality of diode-based memory cells, at least one diode-based dummy memory cell and a plurality of address-select lines;

a plurality of contact vias coupling said address-select lines in said 3D -MPROM levels and said substrate;

wherein said first input is coupled to selected one of said diode-based memory cells through a first selected contact via, and said second input is coupled to said diode-based dummy memory cell through a second selected contact via.

2. The 3D-MPROM according to claim 1, wherein said sense-amplifiers further comprise an S/A-enable (SE) signal, whereby said sense-amplifiers amplify read-out signals from selected ones of said diode-based memory cells when said SE signal is asserted.

3. The 3D-MPROM according to claim 2, further comprising:

a first timing bit line in said 3D-MPROM levels;

a first timing sense-amplifier in said semiconductor substrate and coupled to said first timing bit line;

whereby the output from said first timing sense-amplifier asserts said SE signal and starts data sampling.

4. The 3D-MPROM according to claim 2, further comprising:

a second timing bit line in said 3D-MPROM levels;

a second timing sense-amplifier in said semiconductor substrate and coupled to said second timing bit line;

whereby the output from said second timing sense-amplifier de-asserts said SE signal and stops data sampling.

5. The 3D-MPROM according to claim 1, wherein the read voltage (V_R) applied to said diode-based memory cells is larger than the supply voltage of said 3D-MPROM.

6. The 3D-MPROM according to claim 5, further comprising a V_R-generating block in said semiconductor substrate.