Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin

• US 7,763,943 B2
• Filed: 12/26/2007
• Issued: 07/27/2010
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Kavalieros, Jack T., Rakshit, Titash, Doyle, Brian S., Pillarisetty, Ravi
• Primary Examiner(s): Blum; David S
• Application Number:
  US11/964,623
• Publication Number:
  US 20090166742A1
• Time in Patent Office: 944 Days
• Field of Search: 257/365, 257/E21.421, 257/E21, 257/425, 257/E29.264, 257/E29.275, 257/E29.271, 438/283
• US Class Current: 257/365
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

Claims

1. An apparatus, comprising:

a semiconductor substrate; and

one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, wherein the gate region of the one or more fins comprises a semiconductor material, and wherein the source and drain regions of the one or more fins comprise a metal portion and a semiconductor portion, the metal portion being coupled to the semiconductor portion on a surface of the semiconductor portion that is not coupled to the semiconductor substrate, and the metal portion not being coupled to the semiconductor substrate.

2. An apparatus according to claim 1, wherein the semiconductor substrate is coupled with the semiconductor portion of the source and drain regions of the one or more fins underneath where the semiconductor portion of the source and drain regions are coupled with the metal portion.

3. An apparatus according to claim 1, wherein the metal portion of the source and drain regions is disposed on the semiconductor portion so that an electrical conductivity of the combination of the semiconductor portion and the metal portion in the source and drain regions is increased in comparison the electrical conductivity of just the semiconductor portion of the source and drain regions.

4. An apparatus according to claim 1, wherein the metal portion is formed by a replacement process, the metal portion comprising aluminum, titanium, cobalt, gold, silver, platinum, nickel, alloys or combinations thereof.

5. An apparatus according to claim 1, further comprising a gate stack coupled with the gate region of the one or more fins, wherein the gate stack comprises:

a gate dielectric film coupled with the one or more fins;

a first gate electrode comprising metal coupled with the gate dielectric film; and

a second gate electrode comprising polysilicon coupled with the first gate electrode.

6. An apparatus according to claim 1, wherein the semiconductor material and the semiconductor portion comprise silicon.

7. An apparatus according to claim 1, wherein the multi-gate transistor device is a tri-gate device comprising reduced external resistance (R_ext) in comparison to a tri-gate device comprising only the semiconductor material in the source and drain regions.

8. An apparatus according to claim 2, wherein the metal portion of the source and drain regions is disposed on the semiconductor portion so that an electrical conductivity of the semiconductor portion and the metal portion in the source and drain regions in combination is increased in comparison the electrical conductivity of just the semiconductor portion of the source and drain regions.

9. An apparatus according to claim 8, wherein the metal portion is formed by a replacement process, the metal portion comprising aluminum, titanium, cobalt, gold, silver, platinum, nickel, alloys or combinations thereof.

10. An apparatus according to claim 9, further comprising a gate stack coupled with the gate region of the one or more fins, wherein the gate stack comprises:

a gate dielectric film coupled with the one or more fins;

a first gate electrode comprising metal coupled with the gate dielectric film; and

a second gate electrode comprising polysilicon coupled with the first gate electrode.

11. An apparatus according to claim 10, wherein the semiconductor material and the semiconductor portion comprise silicon.

12. An apparatus according to claim 11, wherein the multi-gate transistor device is a tri-gate device comprising reduced external resistance (R_ext) in comparison to a tri-gate device comprising only the semiconductor material in the source and drain regions.