Post last wiring level inductor using patterned plate process

• US 7,763,954 B2
• Filed: 07/10/2008
• Issued: 07/27/2010
• Est. Priority Date: 07/27/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chinthakindi, Anil Kumar, Florkey, John Edward, He, Zhong-Xiang, Gambino, Jeffrey Peter, Stamper, Anthony Kendall, Vaed, Kunal, Coolbaugh, Douglas Duane
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US12/170,489
• Publication Number:
  US 20080290458A1
• Time in Patent Office: 747 Days
• Field of Search: 257531-535, 257/724, 257/E29.325
• US Class Current: 257/533
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.

Claims

1. A semiconductor structure, comprising:

a substrate having a metal wiring level within the substrate;

a capping layer on and above a top surface of the substrate;

an insulative layer on and above a top surface of the capping layer;

an inductor comprising a first portion in and above the insulative layer and a second portion in and above the insulative layer; and

a wire bond pad within the insulative layer, wherein the first portion of the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer,

wherein a top surface of the first part of the first portion of the inductor and a top surface of the first part of the second portion of the inductor are coplanar.

2. The structure of claim 1, wherein the inductor is a spiral inductor.

3. The structure of claim 1, wherein the inductor is a horizontal inductor.

4. The structure of claim 1, wherein a bottom surface of the insulative layer is in direct mechanical contact with the top surface of the capping layer, and wherein a bottom surface of the capping layer is in direct mechanical contact with at the top surface of the substrate.

5. A semiconductor structure, comprising:

a substrate having a metal wiring level within the substrate;

a capping layer on and above a top surface of the substrate;

an insulative layer on and above a top surface of the capping layer;

an inductor comprising a first portion in and above the insulative layer and a second portion in and above the insulative layer; and

a wire bond pad within the insulative layer, wherein the first portion of the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer,

wherein a bottom surface of the insulative layer is in direct mechanical contact with the top surface of the capping layer, and wherein a bottom surface of the capping layer is in direct mechanical contact with at the top surface of the substrate,

wherein the first portion of the inductor comprises a first part disposed only above the insulative layer, a second part contiguous with the first part of the first portion of the inductor and disposed only above and within the insulative layer, and a third part contiguous with the second part of the first portion of the inductor and disposed within the insulative layer and the capping layer,

wherein the second portion of the inductor comprises a first part disposed only above the insulative layer and a second part contiguous with the first part of the second portion of the inductor and disposed only above and within the insulative layer,

wherein a width of the first part of the first portion of the inductor in a second direction exceeds a width of the second part of the first portion of the inductor in the second direction,

wherein a width of the second part of the first portion of the inductor in the second direction exceeds a width of the third part of the first portion of the inductor in the second direction,

wherein a width of the first part of the second portion of the inductor in the second direction exceeds a width of the second part of the second portion of the inductor in the second direction, and

wherein the second direction is orthogonal to the first direction.

6. The structure of claim 5, wherein a top surface of the first part of the first portion of the inductor and a top surface of the first part of the second portion of the inductor are coplanar.

7. The structure of claim 5, wherein the second part of the second portion of the inductor is above the capping layer and is not in direct mechanical contact with the capping layer.

8. The structure of claim 5, wherein a height of the first part of the first portion of the inductor in the first direction is equal to a height of the first part of the second portion of the inductor in the first direction, and wherein a height of the second part of the first portion of the inductor in the first direction is equal to a height of the second part of the second portion of the inductor in the first direction.

9. The structure of claim 5, wherein the metal wiring level comprises a first conductive wire and a second conductive wire, wherein a top surface of the first conductive wire is in direct mechanical contact with a bottom surface of the third part of the first portion of the inductor, wherein a top surface of the second conductive wire is in direct mechanical contact with a bottom surface of the wire bond pad, and wherein the top surface of the first conductive wire, the top surface of the second conductive wire, and the top surface of the substrate are coplanar.

10. The structure of claim 9, wherein the first conductive wire and the second conductive wire each comprise copper, and wherein the capping layer comprises a diffusion barrier that prevents copper from the first and second conductive wires from diffusing through the capping layer into the insulative layer.