Buffer circuit, buffer tree, and semiconductor device

• US 7,764,085 B2
• Filed: 04/01/2005
• Issued: 07/27/2010
• Est. Priority Date: 07/19/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Satake, Hiroyuki, Takahashi, Hiroyuki
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/097,844
• Publication Number:
  US 20050168243A1
• Time in Patent Office: 1,943 Days
• Field of Search: 326 80- 83, 326/86
• US Class Current: 326/82
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 2005/00136 Avoiding asymmetry of delay for leading or trailing edge; Avoiding variations of delay due to threshold
• CPC Class Codes: H03K 5/086 generated by feedback
• CPC Class Codes: H03K 5/1515 non-overlapping

Abstract

A buffer circuit includes first and second transistors which are connected in series between first and second power supplies and which are controlled to be on/off based on values of signals at their control terminals are provided, in which a connection point between the two transistors is connected to an output terminal (OUT) and a control terminal of the first transistor is connected to an input terminal (IN), and a control circuit for performing on/off control over the second transistor based on an input signal from the input terminal (IN). The control circuit performs control so that when the input signal is at a second logic level corresponding to the second power supply, the second transistor is turned off, when the input signal goes to a first logic level corresponding to the first power supply, the second transistor is turned on to cause the output terminal (OUT) to a second power supply voltage, next, when the second transistor is turned off and then the input signal undergoes a transition from the first logic level to the second logic level and the first transistor switches from off to on, with the second transistor being kept off. A flip-flop is connected to the output terminal (OUT).

Claims

1. A buffer circuit having at least an input terminal for receiving an input signal and an output terminal for outputting an output signal;

said buffer circuit further comprising;

a pulling up transistor and a pulling down transistor connected to said output terminal, respectively pulling up and pulling down said output terminal;

a control circuit connected between said input terminal and said output terminal;

said pulling up transistor directly receiving said input signal through said control circuit receiving an output of said control circuit;

wherein said control circuit causes said pulling up transistor and the pulling down transistor to go from an ON state to an OFF state during a first interval in which the input changes from low to high, while said pulling down transistor is OFF, and during a second interval following the first interval said pulling down transistor is transferred from an OFF state to an ON state and during a third interval following the second interval said pulling down transistor is transferred from said ON state to said OFF state while said pulling up transistor is maintained in said OFF state.

2. A buffer circuit having at least an input terminal for receiving an input signal and an output terminal for outputting an output signal, said buffer circuit further comprising:

a first transistor and a second transistor whose drains being commonly connected to said output terminal, said first and second transistors being connected in series across different power sources; and

a control circuit, wherein said control circuit causes said first transistor to transfer from an ON state to an OFF state during a first interval during which said input signal changes from a Low level to a High level and said second transistor is maintained at an OFF state, and during a second interval following said first interval said second transistor is transferred from the OFF state to the ON state and said first transistor is maintained at the OFF state, and during a third interval following said second interval said second transistor is transferred from the OFF state to the ON state and said first transistor is maintained in the OFF state and during a fourth state following said third state said second transistor is transferred from an ON state to an OFF state, and during a fifth state following said fourth state said first transistor and said second transistor are both maintained in the OFF state, whereby said first transistor and said second transistor are not maintained in said ON state at the same time during any portion of a clock cycle.

3. A clock buffer circuit comprising an input terminal for receiving an input clock signal having a cycle comprising a first clock cycle level and a second clock cycle level, and comprising an output terminal for outputting an output clock signal, said buffer circuit further comprising:

a pull-up pull-down transistor circuit comprising a pull-up transistor and a pull down transistor connected in series between a high voltage supply and a low voltage supply, with a connecting node comprising said clock buffer output terminal, the pull up transistor establishing said first clock cycle level on said clock buffer output terminal and the pull down transistor establishing said second clock cycle level on said clock buffer output terminal;

a control circuit having as an input said input clock signal and a signal derived from a signal on said clock buffer output terminal;

said control circuit controlling a first transistor of said pull-up and pull down transistors to turn on and off in response to said input clock signal to establish with said first transistor said first level on said clock buffer output terminal during a first portion of said clock cycle, and controlling a second transistor of said pull-up and pull down transistors to turn on and off in response to said input clock signal and said signal derived from said signal on said clock buffer output, to establish with said second transistor said second level on said clock buffer output terminal during a second portion of said input clock cycle, a duration of said second level being abbreviated to be less than the remainder of the period of said input clock cycle remaining when said first portion is subtracted from said period, whereby said pull-up and pull-down transistors are controlled to not be on at the same time.

4. The clock buffer circuit of claim 3 wherein:

said first transistor comprises said pull-up transistor, which when on establishes a high voltage signal on said clock buffer output terminal; and

,

said second transistor comprises said pull-down transistor, which when on establishes a low voltage on said clock buffer output terminal.

5. The clock buffer circuit of claim 3 wherein:

said first transistor comprises said pull-down transistor, which when on establishes a low voltage signal on said clock buffer output terminal; and

,

said second transistor comprises said pull-up transistor, which when on establishes a high voltage on said clock buffer output terminal.

6. The clock buffer circuit of claim 4 wherein:

said control circuit comprises logic circuitry to establish the beginning and the end of the duration of said second level of said buffer circuit output which is abbreviated to be less than the remainder of the period of said input clock cycle remaining when said first portion is subtracted from said period based upon the signals on the clock input terminal and the buffer circuit output terminal.

7. The clock buffer circuit of claim 5 wherein:

said control circuit comprises logic circuitry to establish the beginning and the end of the duration of said second level of said buffer circuit output which is abbreviated to be less than the remainder of the period of said input clock cycle remaining when said first portion is subtracted from said period based upon the signals on the clock input terminal and the buffer circuit output terminal.