Auto-correction feedback loop for offset and ripple suppression in a chopper-stabilized amplifier

• US 7,764,118 B2
• Filed: 02/11/2009
• Issued: 07/27/2010
• Est. Priority Date: 09/11/2008
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Kusuda, Yoshinori, Botker, Thomas L.
• Primary Examiner(s): CHOE, HENRY
• Application Number:
  US12/378,204
• Publication Number:
  US 20100060352A1
• Time in Patent Office: 531 Days
• Field of Search: 330/9, 327/124, 327/307
• US Class Current: 330/9
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

A chopper-stabilized amplifier includes a main signal path having first and second chopping circuits at the inputs and outputs of a transconductance amplifier, and an auto-correction feedback loop. The feedback loop includes a transconductance amplifier connected to amplify the chopped output from the main signal path, a third chopping circuit which chops the amplified output, a filter which filters the chopped output to substantially reduce any offset voltage-induced AC component present in the signal being filtered, and a transconductance amplifier which receives the filtered output and produces an output which is coupled back into the main signal path. When properly arranged, the auto-correction feedback loop operates to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in the amplifier'"'"'s output.

Claims

1. A chopper-stabilized amplifier, comprising:

a main signal path, comprising;

an input chopping circuit which receives a differential input signal and chops said input signal in response to a chopping clock, said chopped input signal provided at said input chopping circuit'"'"'s output;

a first transconductance amplifier connected to receive said input chopping circuit'"'"'s output at its input and to produce a first differential output which varies with its input;

an output chopping circuit which receives the first differential output from said first transconductance amplifier and chops said first differential output in response to said chopping clock, said chopped first differential output signal provided at said output chopping circuit'"'"'s output; and

a second transconductance amplifier connected to receive said output chopping circuit'"'"'s output at its input and to produce an output which varies with its input; and

an auto-correction feedback loop, comprising;

a third transconductance amplifier connected to receive said output chopping circuit'"'"'s output at its input and to produce a third differential output which varies with its input;

a third chopping circuit which receives the third differential output from said third transconductance amplifier and chops said third differential output in response to said chopping clock, said chopped third differential output signal provided at said third chopping circuit'"'"'s output;

a filter arranged to filter said third chopping circuit'"'"'s output so as to substantially reduce the AC component present in said chopped third differential output signal and to provide said filtered version of said third chopping circuit'"'"'s output at an output; and

a fourth transconductance amplifier connected to receive said filtered version of said third chopping circuit'"'"'s output at its input and to produce a fourth differential output which varies with its input, said fourth differential output coupled to said first differential output, said auto-correction feedback loop arranged to suppress transconductance amplifier-related offset voltages and offset voltage-induced ripple that might otherwise be present in said output chopping circuit'"'"'s output.

2. The chopper-stabilized amplifier of claim 1, wherein said filter is a switched capacitor notch filter.

3. The chopper-stabilized amplifier of claim 2, wherein said switched capacitor notch filter is clocked with a clock which has the same frequency as said chopping clock and is phase-shifted 90 degrees with respect to said chopping clock.

4. The chopper-stabilized amplifier of claim 3, wherein said switched capacitor notch filter comprises:

first and second input terminals and first and second output terminals;

a first switch connected between said first input terminal and a first capacitance;

a second switch connected between said first output terminal and said first capacitance;

a third switch connected between said first input terminal and a second capacitance;

a fourth switch connected between said first output terminal and said second capacitance;

a fifth switch connected between said second input terminal and a third capacitance;

a sixth switch connected between said second output terminal and said third capacitance;

a seventh switch connected between said second input terminal and a fourth capacitance;

an eighth switch connected between said second output terminal and said fourth capacitance;

said switched capacitor notch filter clock comprising ‘

true’

(SCNF) and ‘

complement’

( SCNF) versions, said first, fourth, fifth and eighth switches closed and said second third, sixth and seventh switches open when SCNF is high and SCNF is low, and said first, fourth, fifth and eighth switches open and said second third, sixth and seventh switches closed when SCNF is high and is SCNF is low.

5. The chopper-stabilized amplifier of claim 1, wherein said filter is a low-pass filter.

6. The chopper-stabilized amplifier of claim 1, further comprising:

a feedforward transconductance amplifier connected to receive said differential input signal at its input and to produce an output which varies with its input and is coupled to the output of said second transconductance amplifier;

a buffer amplifier connected to receive the output of said second transconductance amplifier at its input and to produce an output which varies with its input;

a compensation network connected to provide frequency compensation for said chopper-stabilized amplifier.

7. The chopper-stabilized amplifier of claim 6, wherein said compensation network is a nested mirror compensation network.

8. The chopper-stabilized amplifier of claim 6, wherein said compensation network comprises:

a first capacitor connected between the output of said buffer amplifier and one input of said second transconductance amplifier;

a second capacitor connected between the other input of said second transconductance amplifier and a circuit common point; and

a third capacitor connected between the input and output of said buffer amplifier.

9. The chopper-stabilized amplifier of claim 6, wherein said amplifier is arranged such that said amplifier'"'"'s residual input-referred offset voltage (Vos_res) is given by:

Vos_res=(Vos2+Vosf*Af/A2+Vos4/A3)/A1,

where Vos2, Vosf and Vos4 are the initial offset voltages associated with said second transconductance amplifier, said feedforward amplifier and said fourth transconductance amplifier, respectively, and A1, A2, A3 and Af are the gain values associated with said first, second, third and feedforward transconductance amplifiers, respectively.

10. The chopper-stabilized amplifier of claim 1, said amplifier arranged such that a DC offset voltage associated with said first transconductance amplifier appears as a non-zero DC voltage at the output of said first transconductance amplifier which is converted to an AC voltage by said output chopping circuit, said AC voltage amplified by said third transconductance amplifier and converted to a DC voltage by said third chopping circuit, said DC voltage fed back to said first differential output such that it suppresses the non-zero DC voltage at the output of said first transconductance amplifier induced by said DC offset voltage associated with said first transconductance amplifier.

11. The chopper-stabilized amplifier of claim 1, said amplifier arranged such that a DC offset voltage associated with said third transconductance amplifier appears as a non-zero DC voltage at the output of said third transconductance amplifier which is converted to an AC signal by said third chopping circuit, said filter arranged to filter said third chopping circuit'"'"'s output so as to substantially reduce the magnitude of said AC signal present in said chopped third differential output signal due to said DC offset voltage.

12. The chopper-stabilized amplifier of claim 1, said amplifier arranged such that a DC offset voltage associated with said fourth transconductance amplifier or imperfections in said filter appears as a non-zero DC voltage at the output of said fourth transconductance amplifier, said auto-correction feedback loop arranged to suppress said non-zero DC voltage induced by said DC offset voltage or said imperfections in said filter.