Phase-lock loop startup circuit and voltage controlled oscillator reference generator

• US 7,764,129 B1
• Filed: 12/18/2008
• Issued: 07/27/2010
• Est. Priority Date: 12/18/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Swanson, Richard William, Wong, Anna Wing Wah
• Primary Examiner(s): Chang; Joseph
• Application Number:
  US12/338,368
• Time in Patent Office: 586 Days
• Field of Search: 331/44, 331/11, 331/16
• US Class Current: 331/44
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/146 by using digital means for generating the oscillator control signal H03L7/141, H03L7/143 take precedence

Abstract

A method of startup for a phase-locked loop (PLL) can include, at initiation of the PLL, providing a reference voltage from a startup voltage source to an input of a voltage controlled oscillator (VCO) in the PLL, wherein the reference voltage is set to a predetermined minimum voltage. The reference voltage can be stepwise increased from the predetermined minimum voltage. A frequency of a reference signal input to the PLL can be compared with a frequency of a feedback signal originating from an output of the VCO of the PLL to determine a frequency differential as the reference voltage increases. A determination can be made as to whether a convergence criterion is met according to the frequency differential. While the convergence criterion is not met, the reference voltage can be increased. When the convergence criterion is met, the reference voltage provided by the startup voltage source can be replaced with a voltage generated by an operational voltage source.

Claims

1. A method of startup for a phase-locked loop (PLL), the method comprising:

at initiation of the PLL, providing a reference voltage from a startup voltage source to an input of a voltage controlled oscillator (VCO) in the PLL, wherein the reference voltage is set to a predetermined minimum voltage;

stepwise increasing the reference voltage from the predetermined minimum voltage;

comparing a frequency of a reference signal input to the PLL with a frequency of a feedback signal originating from an output of the VCO of the PLL to determine a frequency differential as the reference voltage increases;

determining whether a convergence criterion is met according to the frequency differential;

while the convergence criterion is not met, increasing the reference voltage; and

when the convergence criterion is met, replacing the reference voltage provided by the startup voltage source with an operational voltage generated by an operational voltage source.

2. The method of claim 1, wherein providing a reference voltage from a startup voltage source further comprises:

operationally disconnecting an output of the operational voltage source from the input of the VCO; and

operationally connecting an output of the startup voltage source to the input of the VCO.

3. The method of claim 1, further comprising determining that the convergence criterion is not met responsive to detecting at least two consecutive transition edges of the reference signal without detecting an intervening transition edge of the feedback signal.

4. The method of claim 1, further comprising determining that the convergence criterion is met when transition edges of the reference signal and the feedback signal alternate for two consecutive periods of the reference signal.

5. The method of claim 1, wherein replacing the reference voltage provided by the startup voltage source with the operational voltage generated by the operational voltage source further comprises:

operationally disconnecting an output of the startup voltage source from the input of the VCO; and

operationally connecting an output of the operational voltage source to the input of the VCO.

6. The method of claim 1, wherein the PLL is in phase and frequency lock, the method comprising:

comparing the operational voltage at the input of the VCO with the reference voltage, wherein the reference voltage is set to the predetermined minimum voltage;

dynamically, stepwise adjusting the reference voltage in increments of a predetermined quantity of voltage according to the comparing of the operational voltage with the reference voltage; and

storing, in memory, a counter value representing the reference voltage that occurs immediately prior to the reference voltage being stepwise adjusted to exceed the operational voltage.

7. The method of claim 6, further comprising:

responsive to detecting a loss of the reference signal to the PLL, recalling the counter value from memory;

setting the reference voltage to a voltage level indicated by the recalled counter value; and

replacing the operational voltage provided to the input of the VCO with the reference voltage.

8. A phase-locked loop (PLL) system comprising a voltage controlled oscillator (VCO) and a voltage reference generator, wherein the reference voltage generator comprises:

a reference voltage source that, at initiation of the PLL system, generates a reference voltage set to a predetermined minimum voltage that is provided to an input of the VCO in the PLL system; and

a controller that stepwise increases the reference voltage of the reference voltage source, compares a frequency of a reference signal provided to the PLL system with a frequency of a feedback signal originating from an output of the VCO, calculates a frequency differential between the reference signal and the feedback signal as the reference voltage increases, and determines whether a convergence criterion is met according to the frequency differential,

wherein, when the convergence criterion is met, the controller disconnects the reference voltage source from the input of the VCO and connects an operational voltage source to the input of the VCO.

9. The system of claim 8, wherein, at startup of the PLL system, the controller opens a feedback loop of the PLL system by connecting the reference voltage source to the input of the VCO in lieu of the operational voltage source.

10. The system of claim 9, wherein the controller operationally disconnects an output of the operational voltage source from the input of the VCO and operationally connects an output of the reference voltage generator to the input of the VCO.

11. The system of claim 8, wherein the controller comprises:

a counter providing a control signal to the reference voltage source controlling the reference voltage output from the reference voltage source; and

a logic block periodically incrementing the counter, thereby stepwise increasing the reference voltage.

12. The system of claim 8, wherein the controller determines that the convergence criterion is not met when two consecutive transition edges are detected in the reference signal without detecting an intervening transition edge in the feedback signal.

13. The system of claim 8, wherein the controller determines that the convergence criterion is met when transition edges of the reference signal and the feedback signal alternate for two consecutive periods of the reference signal.

14. A phase-locked loop (PLL) system, comprising:

an operational voltage source that generates an operational voltage that is provided to an input of a voltage controlled oscillator (VCO) of the PLL system during phase and frequency lock of the PLL system;

a reference voltage source generating a reference voltage; and

a controller that, while the PLL system is in phase and frequency lock, determines whether a reference signal to the PLL system is available and controls the reference voltage source to generate the reference voltage approximating the operational voltage from the operational voltage source, wherein the controller selectively stores a count value, indicating the reference voltage, in memory,

wherein, responsive to determining that the reference signal is unavailable, the controller operationally disconnects the operational voltage source from the input of the VCO, recalls the count value from memory, controls the reference voltage source to generate the reference voltage having a voltage corresponding to the recalled count value, and operationally connects the reference voltage source to the input of the VCO.

15. The PLL system of claim 14, wherein, responsive to determining that the reference signal is available, the controller operationally disconnects the reference voltage source from the input of the VCO and operationally connects the operational voltage source to the input of the VCO.

16. The PLL system of claim 14, wherein, responsive to determining that the reference signal is unavailable, the controller opens a feedback loop of the PLL system by connecting the reference voltage source to the input of the VCO in lieu of the operational voltage source.

17. The PLL system of claim 14, wherein the controller comprises a comparator that compares the operational voltage generated by the operational voltage source at the input of the VCO during phase and frequency lock of the PLL system with the reference voltage generated by the reference voltage source.

18. The PLL system of claim 17, wherein the controller comprises a logic block and a counter maintaining the count value, wherein responsive to a comparison signal generated by the comparator, the logic block decrements the count value of the counter when the reference voltage exceeds the operational voltage and increments the count value of the counter when the operational voltage exceeds the reference voltage.

19. The PLL system of claim 18, wherein the counter outputs a control signal causing the reference voltage source to increase the reference voltage or decrease the reference voltage according to the count value.

20. The PLL system of claim 14, wherein the controller, responsive to determining that the reference voltage has transitioned from a first voltage level less than the operational voltage to a second voltage level exceeding the operational voltage, stores the count value corresponding a the first voltage level in memory.