All digital frequency-locked loop circuit method for clock generation in multicore microprocessor systems
First Claim
1. A digital frequency locked-loop (DFLL) circuit residing on a local core of a multi-core microprocessor system for generating a local core clock with a frequency value for driving the local core, comprising:
- a micro-controller configured to receive a plurality of digital data for characterizing the local core;
a digitally-controlled ring oscillator configured to generate the local core clock for the local core, the digitally-controlled ring oscillator having a delay chain disposed between an output of the digitally-controlled ring oscillator and a feedback input of the digitally-controlled ring oscillator, the delay chain having a plurality of delay taps each receiving the local core clock from the output through the feedback input of the digitally-controlled ring oscillator for enabling single or multi-step quantum changes in the frequency value of the local core clock; and
a counter device configured to continually validate the frequency value of the local core clock by generating a digital signal representative of the frequency value to the micro-controller, the micro-controller compares the frequency value of the local core clock to a desired clock frequency when the micro-controller receives the digital signal from the counter device, and the micro-controller selects one of the plurality of delay taps based on the comparison to adjust the frequency value of the local core clock towards alignment with the desired clock frequency.
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Abstract
A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock.
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Citations
20 Claims
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1. A digital frequency locked-loop (DFLL) circuit residing on a local core of a multi-core microprocessor system for generating a local core clock with a frequency value for driving the local core, comprising:
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a micro-controller configured to receive a plurality of digital data for characterizing the local core; a digitally-controlled ring oscillator configured to generate the local core clock for the local core, the digitally-controlled ring oscillator having a delay chain disposed between an output of the digitally-controlled ring oscillator and a feedback input of the digitally-controlled ring oscillator, the delay chain having a plurality of delay taps each receiving the local core clock from the output through the feedback input of the digitally-controlled ring oscillator for enabling single or multi-step quantum changes in the frequency value of the local core clock; and a counter device configured to continually validate the frequency value of the local core clock by generating a digital signal representative of the frequency value to the micro-controller, the micro-controller compares the frequency value of the local core clock to a desired clock frequency when the micro-controller receives the digital signal from the counter device, and the micro-controller selects one of the plurality of delay taps based on the comparison to adjust the frequency value of the local core clock towards alignment with the desired clock frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for tuning the frequency of a local core clock configured to drive a local core in a multi-core microprocessor system, the method comprising:
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disposing a digital frequency locked-loop (DFLL) circuit on the local core; generating a digital signal representative of the frequency of the local core clock to a micro-controller of the DFLL circuit when the frequency of the local core clock is validated by a counter device of the DFLL circuit; comparing the frequency of the local core clock to a desired clock frequency when the micro-controller receives the digital signal from the counter device; and selecting one of a plurality of delay taps of a delay chain in a digitally controlled ring oscillator of the DFLL circuit based on the comparison to adjust the frequency of the local core clock towards alignment with the desired clock frequency, the plurality of delay taps each receive the local core clock from an output end of the digitally controlled ring oscillator, the plurality of delay taps enable single or multi-step quantum changes in the frequency of the local core clock. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification