Method of programming a non-volatile memory

• US 7,764,550 B2
• Filed: 11/25/2008
• Issued: 07/27/2010
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Baker, Jr., Frank K., Chindalore, Gowrishankar L., Suhail, Mohammed
• Primary Examiner(s): Mai, Son L
• Application Number:
  US12/277,404
• Publication Number:
  US 20100128537A1
• Time in Patent Office: 609 Days
• Field of Search: 365/185.28
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when any set of cells of the memory system have been erased a specific number of times.

Claims

1. A memory system, comprising:

a plurality of non-volatile memory cells, each memory cell of the plurality is programmable and erasable;

program circuitry for programming memory cells of the plurality of non-volatile memory cells, the program circuitry programs memory cells of the plurality to above a first program threshold voltage in response to a first mode and to above a second program threshold voltage in response to a second mode, wherein the first program threshold voltage is different than the second program threshold voltage;

erase circuitry for erasing cells of the plurality of non-volatile memory cells;

a count circuit, the count circuit including an erase count value; and

count increment circuitry for incrementing the erase count value in response to an erase operation of the plurality of memory cells when in the first mode, wherein the first mode transitions to the second mode in response to the erase count value reaching a specific value.

2. The memory system of claim 1, further comprising:

a second plurality of non-volatile memory cells, each memory cell of the second plurality is programmable and erasable;

wherein the program circuitry programs memory cells of the second plurality of non-volatile memory cells, the program circuitry programs memory cells of the second plurality to above the first program threshold voltage in response to the first mode and to above the second program threshold voltage in response to the second mode; and

a second count circuit including a second erase count value;

wherein the second erase count value is incremented in response to an erase operation of the second plurality of memory cells during the first mode, wherein the first mode transitions to the second mode in response to the second erase count value reaching the specific value.

3. The memory system of claim 2, wherein the first plurality of memory cells and the second plurality of memory cells are located in an array of memory cells.

4. The memory system of claim 2, wherein the count increment circuitry increments the first erase count value to the specific value in response to the second erase count value reaching the specific value.

5. The memory system of claim 2, further comprising:

a first array of non-volatile memory cells, the plurality of non-volatile memory cells is implemented in the first array, the program circuitry including circuitry for programming memory cells of the first array; and

a second array of non-volatile memory cells, the second plurality of non-volatile memory cells is implemented in the second array, the program circuitry including circuitry for programming memory cells of the second array.

6. The memory system of claim 2, further comprising:

a third plurality of non-volatile memory cells, each memory cell of the third plurality is programmable and erasable;

wherein the program circuitry programs memory cells of the third plurality of non-volatile memory cells, the program circuitry programs memory cells of the third plurality to above the first program threshold voltage in response to the first mode and to above the second program threshold voltage in response to the second mode;

a third count circuit including a third erase count value; and

wherein the third erase count value is incremented in response to an erase operation of the third plurality of memory cells during the first mode, wherein the first mode transitions to the second mode in response to the third erase count value reaching the specific value.

7. The memory system of claim 1, wherein the specific value is in a range of 8-12.

8. The memory system of claim 1, wherein:

the program circuitry programs a cell of the plurality of non-volatile memory cells by storing charge in a charge storage structure of the memory cell,

the programming circuit programs a memory cell to above the first program threshold voltage in response to the first mode by storing charge in the charge storage structure such that a voltage threshold of the memory cell is above the first threshold voltage;

the programming circuit programs a memory cell to above the second program threshold voltage in response to the second mode by storing charge in the charge storage structure such that the voltage threshold of the memory cell is above the second threshold voltage.

9. The memory system of claim 1, wherein the plurality of non-volatile memory cells is implemented in a first location of a memory array of non-volatile memory cells, wherein the count circuit is implemented in a second location of the memory array.

10. The memory system of claim 1, wherein each memory of the plurality of non-volatile memory cells includes a charge storage structure including nitride.

11. A memory system, comprising:

a plurality of sets of non-volatile memory cells, each memory cell of the plurality of sets is programmable and erasable;

program circuitry for programming memory cells of the plurality of sets, the program circuitry programs memory cells of the plurality of sets to above a first program threshold voltage in response to the memory system being in a first mode and to above a second program threshold voltage in response to the memory system being in a second mode;

erase circuitry for erasing memory cells of the plurality of sets;

a plurality of count circuits each for storing an erase count for each set of the plurality of sets; and

count increment circuitry for incrementing erase count values of the plurality of count circuits, the count increment circuitry incrementing a count circuit associated with a set of the plurality of sets in response to an erase operation of the set during the first mode, wherein the first mode transitions to the second mode based upon any erase count value of the plurality of count circuits reaching a specific value.

12. The memory system of claim 11, wherein the specific value is in a range of 8-12.

13. The memory system of claim 11, wherein the first program threshold voltage is greater than the second program threshold voltage.

14. The memory system of claim 13, wherein:

the program circuitry programs memory cells of the plurality of sets for a first time duration, at a first voltage of a gate type, and at a first source voltage in response to the memory system being in the first mode; and

the program circuitry programs memory cells of the plurality of sets for a second time duration, at a second voltage of the gate type, and at a second source voltage in response to the memory system being in the second mode;

wherein the program circuitry comprises one characteristic of a group consisting of;

the first time duration is longer than the second time duration;

the first voltage of the gate type is higher than the second voltage of the gate type;

the first source voltage is higher than the second source voltage;

a source voltage is different between the first mode and the second mode; and

a substrate bias voltage is different between the first mode and the second mode.

15. The memory system of claim 11, further comprising:

a first array of non-volatile memory cells, a first set of the plurality is in the first array;

a second array of non-volatile memory cells, a second set of the plurality is in the second array.

16. The memory system of claim 11, further comprising:

at least one non-volatile memory array, each set of the plurality of sets is located in an array of the at least one memory array;

each count circuit is located in an array of the least one memory array that includes its respective set of the plurality of sets.

17. A method of operating a memory system, wherein the memory system includes a plurality of non-volatile memory cells, the method comprising:

determining whether memory cells of the plurality of non-volatile memory cells have been erased at least a specific number of times; and

programming a memory cell of the plurality of non-volatile memory cells, the programming includes programming the memory cell to above a first program threshold voltage in response to the determining that memory cells have been erased at least a specific number of times, the programming includes programming the memory cell to above a second program threshold voltage in response to the determining that memory cells have not been erased at least the specific number of times, wherein the second threshold voltage is different from the first threshold voltage.

18. The method of claim 17, wherein the second threshold voltage is higher than the first threshold voltage.

19. The method of claim 17, wherein:

the plurality of non-volatile memory cells includes a plurality of sets of non-volatile memory cells;

the determining whether memory cells of the plurality of non-volatile memory cells have been erased at least a specific number of times includes determining whether any set of the plurality of sets has been erased at least the specific number of times;

the programming the memory cell to above the first program threshold voltage in response to the determining that memory cells have been erased at least the specific number of times includes programming the memory cell to above a first program threshold voltage in response to the determining that any set of the plurality of sets has been erased at least the specific number of times; and

the programming the memory cell to above the second program threshold voltage in response to the determining that memory cells have not been erased at least the specific number of times includes the determining that no set of the plurality of sets has been erase the specific number of times.

20. The method of claim 17, wherein the specific number is in a range of 8-12.