Semiconductor memory device having a short reset time
First Claim
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1. A semiconductor memory device, comprising:
- a row path circuit configured to decode a row address signal to provide a word line enable signal to a memory cell array, the row path circuit configured to be initialized in response to a power-up signal;
a reset signal generating circuit configured to delay the power-up signal to generate a column reset signal; and
a column path circuit configured to decode a column address signal to provide a column selection signal to the memory cell array, the column path circuit configured to be initialized in response to the column reset signal, wherein the reset signal generating circuit comprises;
a pulse generator configured to generate a control pulse in response to a command signal; and
a switching circuit configured to transfer the power-up signal to a first node in response to the control pulse.
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Abstract
A semiconductor memory device includes a row path circuit, a reset signal generating circuit and a column path circuit. The row path circuit is initialized in response to a power-up signal. The reset signal generating circuit delays the power-up signal to generate a column reset signal. The column path circuit is initialized in response to the column reset signal. The semiconductor memory device can reduce a peak value of a surge current by initializing a row path circuit and a column path circuit at different time points. Therefore, the semiconductor memory device may have a relatively short setup time of an internal power supply voltage.
14 Citations
22 Claims
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1. A semiconductor memory device, comprising:
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a row path circuit configured to decode a row address signal to provide a word line enable signal to a memory cell array, the row path circuit configured to be initialized in response to a power-up signal; a reset signal generating circuit configured to delay the power-up signal to generate a column reset signal; and a column path circuit configured to decode a column address signal to provide a column selection signal to the memory cell array, the column path circuit configured to be initialized in response to the column reset signal, wherein the reset signal generating circuit comprises; a pulse generator configured to generate a control pulse in response to a command signal; and a switching circuit configured to transfer the power-up signal to a first node in response to the control pulse. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22)
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13. A semiconductor memory device, comprising:
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a row path circuit configured to decode a row address signal to provide a word line enable signal to a memory cell array, the row path circuit configured to be initialized in response to a power-up signal; a reset signal generating circuit configured to delay the power-up signal to generate a column reset signal; and a column path circuit configured to decode a column address signal to provide a column selection signal to the memory cell array, the column path circuit configured to be initialized in response to the column reset signal, wherein the reset signal generating circuit comprises; a switching circuit configured to transfer the power-up signal to a first node in response to a control pulse; a latch circuit configured to latch a voltage signal of the first node; a first inverter configured to invert an output signal of the latch circuit to output the column reset signal; and a pulse generator configured to generate the control pulse in response to a command signal and the column reset signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification