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Semiconductor memory device having a short reset time

  • US 7,764,562 B2
  • Filed: 02/01/2008
  • Issued: 07/27/2010
  • Est. Priority Date: 02/07/2007
  • Status: Active Grant
First Claim
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1. A semiconductor memory device, comprising:

  • a row path circuit configured to decode a row address signal to provide a word line enable signal to a memory cell array, the row path circuit configured to be initialized in response to a power-up signal;

    a reset signal generating circuit configured to delay the power-up signal to generate a column reset signal; and

    a column path circuit configured to decode a column address signal to provide a column selection signal to the memory cell array, the column path circuit configured to be initialized in response to the column reset signal, wherein the reset signal generating circuit comprises;

    a pulse generator configured to generate a control pulse in response to a command signal; and

    a switching circuit configured to transfer the power-up signal to a first node in response to the control pulse.

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