Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit

• US 7,765,074 B2
• Filed: 06/02/2006
• Issued: 07/27/2010
• Est. Priority Date: 02/11/2003
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Stonecypher, William, Zerbe, Jared, Horowitz, Mark, Kim, Dennis
• Primary Examiner(s): Wachsman; Hal D
• Assistant Examiner(s): O MALLEY, MARY CATHERINE
• Application Number:
  US11/445,702
• Publication Number:
  US 20060224339A1
• Time in Patent Office: 1,516 Days
• Field of Search: 702/66, 702/79, 702/90, 702/189, 702124-125, 702176-178, 375/355, 375/371, 375/373, 375375-376, 370/276, 370/360, 370364-365, 370/442, 370/503, 370/516, 360/27, 360/48, 360/51, 341/100
• US Class Current: 702/66
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

Claims

1. A clock data recovery (CDR) circuit, comprising:

a plurality of samplers to receive a data signal;

a phase detector to output CDR tracking information based on information from at least one of the plurality of samplers; and

logic to receive the CDR tracking information and to adjust a phase of a first clock signal used by at least one of the plurality of samplers to sample the data signal, the logic switching between phase locking the first clock signal with the data signal and phase sweeping the first clock signal to allow the CDR circuit to capture a waveform of the data signal in response to a control signal.

2. The CDR circuit of claim 1, wherein the plurality of samplers includes at least one first sampler and the phase detector outputs the CDR tracking information based on information from the at least one first sampler.

3. The CDR circuit of claim 2, wherein the plurality of samplers includes at least one second sampler coupled to the logic to capture the waveform of the data signal.

4. The CDR circuit of claim 3, further comprising additional logic to adjust a phase of at least one second clock signal used by the at least one first sampler to sample the data signal.

5. The CDR circuit of claim 4, wherein the at least one second clock signal is independent of the first clock signal such that the at least one second clock signal continues to phase track the data signal while the first clock signal is phase-swept.

6. The CDR circuit of claim 4, wherein the at least one first sampler, the phase detector and the additional logic form at least part of a CDR loop and the CDR loop is not disengaged when the first clock signal is phase swept to allow the CDR circuit to capture the waveform of the data signal.

7. The CDR circuit of claim 1, wherein at least one of the plurality of samplers, the phase detector and the logic form at least part of a CDR loop and the CDR loop is disengaged when the logic is phase sweeping the first clock signal.

8. The CDR circuit of claim 1, wherein at least one of the plurality of samplers, the phase detector and the logic form at least part of a CDR loop and the CDR loop is not disengaged when the logic is phase sweeping the first clock signal.

9. The CDR circuit of claim 1, wherein the logic also adjusts a phase of a second clock signal used by another one of the plurality of samplers to sample the data signal, the logic keeping the second clock signal phase locked to the data signal while phase-sweeping the first clock signal.

10. The CDR circuit of claim 9, wherein the logic ignores information from the at least one sampler that uses the first clock signal to sampler data when the first clock signal is phase swept.

11. The CDR circuit of claim 9, wherein the another one of the plurality of samplers outputs edge information on even edges of the second clock signal and half-rate data information on odd edges of the second clock signal.

12. A method performed by a clock data recovery (CDR) circuit, comprising:

receiving a data signal at a plurality of samplers;

generating CDR tracking information based on information from at least one of the plurality of samplers;

phase tracking a first clock signal with the data signal based on the CDR tracking information in response to a control signal being de-asserted; and

phase sweeping the first clock signal to capture a waveform of the data signal in response to the control signal being asserted, the first clock signal being used to clock one of the plurality of samplers.

13. The method of claim 12, wherein the CDR tracking information is generated based on information from at least one first sampler.

14. The method of claim 13, wherein the waveform of the data signal is captured by at least one second sampler.

15. The method of claim 12, further comprising phase tracking a second clock signal with the data signal based on the CDR tracking information irrespective of whether the control signal is asserted, the second clock signal being used to clock at least one of the plurality of samplers.

16. The method of claim 15, wherein the CDR tracking information is generated from at least one sampler clocked by the second clock signal.

17. The method of claim 15, wherein the CDR tracking information is not based on information from any of the plurality of samplers clocked by the first clock signal when the control signal is asserted.

18. The method of claim 15, wherein the at least one of the plurality of samplers clocked by the second clock signal outputs edge information on even edges of the second clock signal and half-rate data information on odd edges of the second clock signal.

19. The method of claim 12, further comprising disengaging a CDR loop of the CDR circuit in response to the control signal being asserted.

20. The method of claim 12, further comprising keeping a CDR loop of the CDR circuit running when the first clock signal is phase-swept to capture the waveform of the data signal.