Conditional branching in an in-circuit emulation system

• US 7,765,095 B1
• Filed: 11/01/2001
• Issued: 07/27/2010
• Est. Priority Date: 10/26/2000
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Nemecek, Craig
• Primary Examiner(s): PROCTOR, JASON SCOTT
• Application Number:
  US10/002,217
• Time in Patent Office: 3,190 Days
• Field of Search: 703/28, 703/26, 714/28, 714/11, 712/234, 712/237
• US Class Current: 703/26
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

An In-Circuit Emulation system. A real microcontroller (device under test) operates in lock-step with a virtual microcontroller so that registers, memory locations and other debugged data can be retrieved from the virtual microcontroller without disrupting operation of a real microcontroller. When an I/O read instruction is carried out followed by a conditional jump instruction dependent upon the I/O read data, the virtual microcontroller does not have adequate time to compute the jump address after receipt of I/O read data from the real microcontroller. Thus, when this sequence of instructions is detected, the virtual microcontroller pre-calculates the jump address and makes the jump decision after receipt of the I/O read data from the real microcontroller.

Claims

1. An in-circuit emulation system, comprising:

a microcontroller, wherein said microcontroller sends I/O read data to a virtual microcontroller, and wherein said I/O read data is processed by an instruction in the virtual microcontroller, said instruction is followed by a conditional jump instruction that resides on said virtual microcontroller;

said virtual microcontroller coupled to the microcontroller, wherein said virtual microcontroller has means for detecting said I/O read data, and further has means for computing a speculative conditional jump address before a condition for said conditional jump instruction is satisfied after receipt of said I/O read data; and

the virtual microcontroller further having means for determining after receipt of the I/O read data from the microcontroller whether to proceed with instruction execution at a next consecutive address or at the speculative conditional jump address, wherein said virtual microcontroller executes instructions at said next consecutive address or at said speculative conditional jump address based on said means for determining such that said microcontroller and said virtual microcontroller remain in lockstep by executing the same instruction using the same clocking signal.

2. The apparatus according to claim 1, wherein the conditional jump address is computed while the I/O read data are sent from the microcontroller to the virtual microcontroller.

3. The apparatus according to claim 1, wherein the microcontroller sets a zero flag if an I/O read test condition is met.

4. The apparatus according to claim 3, wherein the jump condition is met if the zero flag is set.

5. The apparatus according to claim 1, wherein the virtual microcontroller is implemented in a Field Programmable Gate Array.

6. A method of handling conditional jumps in a virtual microcontroller operating in lock-step with a microcontroller, comprising:

detecting an I/O read data sent by said microcontroller, wherein said I/O read data is processed by an instruction in the virtual microcontroller, said instruction is followed immediately by a conditional jump instruction that resides on said virtual microcontroller;

after receipt of said I/O read data, computing a speculative conditional jump address before a condition for said conditional jump instruction is satisfied;

after receipt of the I/O read data from the microcontroller, determining whether a conditional jump condition is met; and

executing instruction based on said determination, such that said virtual microcontroller remains in lock-step execution with said microcontroller.

7. The method according to claim 6, wherein said executing comprises execution of next consecutive instruction in the event said conditional jump condition is not met.

8. The method according to claim 6, wherein said executing comprises execution of an instruction at the speculative conditional jump address in the event the conditional jump condition is met.

9. The method according to claim 6, wherein the conditional jump address is computed while the I/O read data are sent from the microcontroller to the virtual microcontroller.

10. The method according to claim 6, wherein the microcontroller sets a zero flag if an I/O read test condition is met.

11. The method according to claim 10, wherein the jump condition is met if the zero flag is set.

12. The method according to claim 6, wherein the virtual microcontroller is implemented in a Field Programmable Gate Array.

13. The method according to claim 6, wherein instructions are stored in an electronic storage medium for execution as program steps on a programmed processor forming a part of the virtual microcontroller.

14. A method of handling conditional jumps in a virtual processor operating in lock-step with a device under test, comprising:

detecting an I/O read data sent by said device under test, wherein said I/O read data is processed by an instruction in the virtual processor, said instruction is followed immediately by a conditional jump instruction that resides on said virtual processor;

after receipt of said I/O read data, computing a speculative conditional jump address before a condition for said conditional jump instruction is satisfied;

after receipt of the I/O read data from the device under test, determining whether a conditional jump condition is met; and

executing instruction based on said determination, such that said virtual processor remains in lock-step execution with said device under test.

15. The method according to claim 14, wherein said executing comprises execution of next consecutive instruction in the event said conditional jump condition is not met.

16. The method according to claim 14, wherein said executing comprises execution of an instruction at the speculative condition jump address in the event the conditional jump condition is met.

17. The method according to claim 14, wherein the conditional jump address is computed while the I/O read data are sent from the device under test to the virtual processor.

18. The method according to claim 14, wherein the device under test sets a zero flag if an I/O read test condition is met.

19. The method according to claim 18, wherein the jump condition is met if the zero flag is set.

20. The method according to claim 14, wherein the virtual processor is implemented in a Field Programmable Gate Array.