Autonomous mapping of protected data streams to fibre channel frames

• US 7,765,336 B2
• Filed: 06/11/2007
• Issued: 07/27/2010
• Est. Priority Date: 06/11/2007
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Emulex Design & Manufacturing Corp. (Broadcom, Inc.)
• Inventors: Tien, Joe Chung-Ping, Butler, Jim Donald, Jin, Daming
• Primary Examiner(s): Hafiz; Tariq
• Assistant Examiner(s): Vidwan; Jasjit S
• Application Number:
  US11/811,716
• Publication Number:
  US 20080307122A1
• Time in Patent Office: 1,142 Days
• Field of Search: 710/2, 710/3, 710/5, 710/20, 710/22, 710/31, 709/220, 709/223
• US Class Current: 710/20
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload

Abstract

A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.

Claims

1. An apparatus for transmitting data between a host and a target over a frame-based communications network, comprising:

a local processor configured for receiving a data transmission request from the host or the target to transmit data over the frame-based communications network;

one or more hardware-based frame transmit engines coupled to the processor, each frame transmit engine configured for, in response to the request received at the processor, automatically mapping the data into frames to be transmitted without involving the processor, wherein each frame transmit engine is further configured for;

determining one or more addresses, byte counts and a protection scheme of the data to be transmitted in a particular sequence of frames,

determining a frame size of the frames to be transmitted,

determining one or more free frame buffers for storing the frames prior to transmission,

generating and storing headers for the frames to be transmitted, and

combining the headers, data and check bytes determined by the protection scheme into the frames for transmission over the network; and

a direct memory access (DMA) engine coupled to the one or more frame transmit engines and configured for reading the data to be transmitted in accordance with the addresses and byte counts determined by one of the frame transmit engines, calculating the check bytes for the data in accordance with the protection scheme, and storing the data and check bytes into the one or more free frame buffers in a local memory accessible to the processor.

2. The apparatus of claim 1, further comprising one or more host data descriptor lists, each host data descriptor list accessible to each frame transmit engine and configured for storing the addresses and byte counts of the data to be transmitted.

3. The apparatus of claim 2, further comprising a protection information/scratch area accessible to the one or more frame transmit engines for storing the frame size and protection scheme of the data to be transmitted.

4. The apparatus of claim 3, further comprising a free buffer pool accessible to the one or more frame transmit engines for identifying the one or more free frame buffers.

5. The apparatus of claim 4, each frame transmit engine comprising a DMA completion frame builder configured for receiving a frame completion message from the DMA engine and generating a header for a frame to be transmitted.

6. The apparatus of claim 5, each frame transmit engine comprising link logic configured for receiving the header from the DMA completion frame builder, storing the header in a location specified by a free frame buffer, assembling a completed frame with the header, data and check bytes, and sending the completed frame out over the communications network.

7. The apparatus of claim 6, each frame transmit engine comprising a frame completion state machine configured for receiving the frame completion message from the link logic and sending a message to the local processor—

when the sequence of frames being handled by the frame transmit engine is to be terminated.

8. The apparatus of claim 3, each frame transmit engine comprising a DMA state machine configured for reading an appropriate host data descriptor list to determine the addresses and byte counts of the host data to be transmitted, and reading the protection information/scratch area to determine the protection scheme and frame size of the data to be transmitted.

9. A host bus adapter (HBA) comprising the apparatus of claim 1.

10. A host computer comprising the HBA of claim 9.

11. A storage area network (SAN) comprising the host computer of claim 10.

20. The apparatus of claim 1, further comprising firmware configured to initiate the frame transmit engineers to perform automatic mapping of the data into the frames without involving the processor.

12. A method for transmitting data between a host and a target over a frame-based communications network, the host coupled to a host bus adapter including a local processor and a frame transmit engine coupled thereto, the frame transmit engine configured to automatically map the data into frames to be transmitted without any involvement of the local processor, the frame transmit engine further configured to perform the method comprising:

determining one or more addresses and byte counts of the data to be transmitted in a particular sequence of frames, determining a protection scheme and a frame size of the host data to be transmitted in the particular sequence of frames, and determining one or more free frame buffers for storing the frames prior to transmission;

communicating with a direct memory access (DMA) engine configured for reading the data to be transmitted in accordance with the determined addresses and byte counts, calculating check bytes for the data in accordance with the protection scheme, and storing the data and check bytes into the one or more free frame buffers;

generating and storing headers for the frames to be transmitted; and

combining the headers, data and check bytes into the frames for transmission over the network.

13. The method of claim 12, wherein the host bus adapter further comprises firmware configured to initiate the frame transmit engineers to perform automatic mapping of the data into the frames without involving the processor.

14. The method of claim 13, further comprising determining the addresses and byte counts of the data to be transmitted in the particular sequence of frames from a host data descriptor list accessible to the frame transmit engine.

15. The method of claim 14, further comprising determining the protection scheme and the frame size of the data to be transmitted in the particular sequence of frames from a protection information/scratch area accessible to the frame transmit engine.

16. The method of claim 15, further comprising determining the one or more free frame buffers for storing the frames prior to transmission from a free buffer pool accessible to the frame transmit engine.

17. The method of claim 15, further comprising storing the frame size and the protection scheme for the data in the protection information/scratch area.

18. The method of claim 14, further comprising storing the addresses and byte counts for the data into the host data descriptor list.

19. The method of claim 13, further comprising sending a sequence termination message to the local processor when the transmission of the sequence of frames is to be terminated.