Hardware multithreading systems with state registers having thread profiling data

• US 7,765,547 B2
• Filed: 11/24/2004
• Issued: 07/27/2010
• Est. Priority Date: 11/24/2004
• Status: Active Grant

• Current Assignee: Geo Semiconductor Incorporated
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Monsen, Kristan J., Cismas, Sorin C., Garbacea, Ilie
• Primary Examiner(s): An; Meng-Ai
• Assistant Examiner(s): Tang; Kenneth
• Application Number:
  US10/996,691
• Publication Number:
  US 20060117316A1
• Time in Patent Office: 2,071 Days
• Field of Search: 718/100, 718/102, 718/103, 718/107, 718/108, 712/214, 712/228, 714/12
• US Class Current: 718/100
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/463 Program control block organisation
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities. A hardware thread profiler including global, run and wait profiler registers is used to monitor thread performance to facilitate software development.

Claims

1. A multithreaded microcontroller comprising:

a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads;

thread control logic connected to the set of multithreading registers, comprising;

thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads; and

thread instructions execution logic connected to the set of thread state registers and configured to execute a set of multithreading system call machine code instructions; and

a hardware thread profiler connected to the set of multithreading registers, the thread profiler comprising thread profiling logic configured to collect thread profiling data for the plurality of threads, the thread profiling data comprising at least one datum selected from a group consisting of a set of state transition counts, an amount of time spent by a thread in a subset of thread states, and a set of thread priority raise counts.

2. The multithreaded microcontroller of claim 1, wherein:

the set of multithreading registers further includes a plurality of thread register sets;

each thread register set corresponds to a thread from the plurality of threads; and

said each thread register set comprises a thread priority field identifying a priority of the thread.

3. The multithreaded microcontroller of claim 2, wherein said each thread register set comprises a mutex field identifying a mutex locked by the thread.

4. The multithreaded microcontroller of claim 2, wherein said each thread register set comprises a condition variable field identifying a condition variable the thread is waiting on.

5. The multithreaded microcontroller of claim 1, wherein the set of multithreading registers further includes a global configuration register identifying a maximum number of threads, a maximum number of mutexes, a maximum number of condition variables, and a maximum number of priorities supported by the microcontroller.

6. The multithreaded microcontroller of claim 5, wherein the set of multithreading registers further includes a global mutex lock register comprising a plurality of mutex lock fields each identifying a locking state of a corresponding mutex from a plurality of mutexes.

7. The multithreaded microcontroller of claim 1, wherein the set of multithreading registers further includes a microcontroller main state register comprising:

a call code field identifying a type for an event that has caused an entry into a system thread; and

a calling thread identification field identifying a calling thread causing the entry into the system thread.

8. The multithreaded microcontroller of claim 7, wherein the microcontroller main state register further comprises a trap code field identifying an opcode for the event that has caused the entry into the system thread.

9. The multithreaded microcontroller of claim 1, wherein the set of multithreading registers comprises a plurality of mutex registers storing a plurality of mutex states for a corresponding plurality of mutexes.

10. The multithreaded microcontroller of claim 1, wherein the set of multithreading registers comprises a plurality of condition variable registers storing a plurality of condition states for a corresponding plurality of condition variables.

11. The multithreaded microcontroller of claim 1, wherein the plurality of processing threads comprises a plurality of processing threads, and a system thread non-interruptible by the processing threads.

12. The multithreaded microcontroller of claim 1, wherein the thread state transition logic comprises logic configured to:

transition a state of a thread from a ready state to a run state when the thread is scheduled for execution;

transition the state of the thread from the run state to an interrupt wait state when the thread receives an interrupt;

transition the state of the thread from the run state to a condition wait state when the thread executes a wait condition instruction;

transition the state of the thread from the run state to a mutex wait state when the thread executes a lock mutex instruction;

transition the state of the thread from the run state to an wait instruction cache state when the thread receives an instruction cache miss signal; and

transition the state of the thread from the run state to a wait memory state when the thread receives a data miss signal.

13. The multithreaded microcontroller of claim 1, wherein the thread instructions execution logic comprises mutex locking logic configured to execute a set of mutex locking instructions.

14. The multithreaded microcontroller of claim 13, wherein the set of mutex locking instructions comprises a committed lock mutex instruction.

15. The multithreaded microcontroller of claim 14, wherein executing the committed lock mutex instruction comprises checking a mutex register to determine whether a mutex identified by the committed lock mutex instruction is locked by a thread executing the committed lock mutex instruction.

16. The multithreaded microcontroller of claim 15, wherein executing the committed lock mutex instruction further comprises:

when the mutex identified by the committed lock mutex instruction is not locked by a thread executing the committed lock mutex instruction, checking a thread priority register to compare a priority of the thread executing the committed lock mutex instruction to a priority of a thread holding a lock of the mutex identified by the committed lock mutex instruction; and

when the priority of the thread executing the committed lock mutex instruction is higher than the priority of the thread holding the lock, increasing the priority of the thread holding the lock to at least the priority of the thread executing the committed lock mutex instruction.

17. The multithreaded microcontroller of claim 14, wherein the set of mutex locking instructions further comprises a test mutex instruction.

18. The multithreaded microcontroller of claim 17, wherein executing the test mutex instruction comprises checking a mutex register to determine whether a mutex identified by the test mutex instruction is locked by a thread executing the test mutex instruction.

19. The multithreaded microcontroller of claim 17, wherein the set of mutex locking instructions further comprises an unlock mutex instruction.

20. The multithreaded microcontroller of claim 13, wherein the set of mutex locking instructions comprises an unlock mutex instruction, and wherein executing the unlock mutex instruction comprises checking a mutex register to determine whether a mutex identified by the unlock mutex instruction is locked by a thread executing the unlock mutex instruction.

21. The multithreaded microcontroller of claim 20, wherein executing the unlock mutex instruction further comprises:

determining whether a set of threads other than the thread executing the unlock mutex instruction are waiting for the mutex identified by the unlock mutex instruction; and

when the set of threads other than the thread executing the unlock mutex instruction are waiting for the mutex identified by the unlock mutex instruction, selecting a highest-priority thread from the set of threads other than the thread executing the unlock mutex instruction, and setting a priority of the highest-priority thread at least as high as a priority of the thread executing the unlock mutex instruction.

22. The multithreaded microcontroller of claim 21, wherein executing the unlock mutex instruction further comprises:

when the set of threads other than the thread executing the unlock mutex instruction are waiting for the mutex identified by the unlock mutex instruction, determining a highest priority among a set of threads waiting for any mutex held by the thread executing the unlock mutex instruction; and

setting the priority of the thread executing the unlock mutex instruction at least as high as the highest priority among the set of threads waiting for any mutex held by the thread executing the unlock mutex instruction.

23. The multithreaded microcontroller of claim 1, wherein the thread instructions execution logic comprises wait condition logic configured to execute a wait condition instruction.

24. The multithreaded microcontroller of claim 23, wherein executing the wait condition instruction comprises checking a mutex register to determine whether a mutex identified by the wait condition instruction is locked by a thread executing the wait condition instruction.

25. The multithreaded microcontroller of claim 23, wherein executing the wait condition instruction comprises transitioning a state of a thread executing the wait condition instruction from a run state to a condition wait state.

26. The multithreaded microcontroller of claim 1, wherein the thread instructions execution logic comprises condition signal logic configured to execute a condition signal instruction.

27. The multithreaded microcontroller of claim 25, wherein executing the condition signal instruction comprises transitioning a state of a thread waiting for a condition signal from a condition wait state to a ready state.

28. The multithreaded microcontroller of claim 1, further comprising thread scheduling logic connected to the set of multithreading registers and configured to schedule the plurality of threads for execution according to the plurality of thread states and a corresponding plurality of thread priorities.

29. The multithreaded microcontroller of claim 1, wherein the thread profiling data includes the set of state transition counts.

30. The multithreaded microcontroller of claim 1, wherein the thread profiling data includes the amount of time spent by the thread in the subset of thread states.

31. The multithreaded microcontroller of claim 1, wherein the thread profiling data includes of thread priority raise counts.

32. The multithreaded microcontroller of claim 1, wherein the thread profiling data includes a set of wait state counts.

33. The multithreaded microcontroller of claim 1, wherein the thread profiler comprises:

a set of thread run profiling units configured to collect run profiling data for the plurality of threads; and

a set of thread wait profiling units configured to collect wait profiling data for the plurality of threads.

34. The multithreaded microcontroller of claim 1, wherein the set of multithreading registers comprises a set of thread profiling registers configured to store thread profiling data for the plurality of threads.

35. The multithreaded microcontroller of claim 1, wherein the set of multithreading registers further includes a thread hardware execution mask register configured to store a thread hardware execution mask corresponding to the set of multithreading system call machine code instructions, the thread hardware execution mask identifying a subset of multithreading system call instructions to be executed in hardware by the thread instructions execution logic, and a subset of multithreading system call instructions to be executed in software by a system thread.

36. The multithreaded microcontroller of claim 1, further comprising an instruction fetching unit connected to the thread control logic and configured to receive a set of machine-code instructions for the plurality of threads, the set of machine-code instructions including a set of arithmetic and logical instructions, and the set of multithreading system call instructions.

37. The multithreaded microcontroller of claim 36, wherein the set of instructions includes a set of conditional jump instruction, wherein at least one conditional jump instruction immediately follows and is conditioned on an outcome of a multithreading system call instruction.

38. The multithreaded microcontroller of claim 1, wherein the set of multithreading registers comprises a set of flag registers storing a set of flags reflecting an outcome of an execution of a latest multithreading system call machine code instruction.

39. The multithreaded microcontroller of claim 38, wherein the set of flags comprise at least one condition flag defining a condition for a conditional jump instruction immediately following the latest multithreading system call machine code instruction.

40. A multithreaded data processing method comprising:

storing a plurality of thread states for a corresponding plurality of threads in a set of thread state registers;

controlling thread state transitions for the plurality of threads using thread state transition logic connected to the set of thread state registers;

executing a set of multithreading system call machine code instructions using thread instructions execution logic connected to the set of thread state registers; and

collecting thread profiling data for the plurality of threads using a hardware thread profiler connected to the set of thread state registers, the thread profiling data comprising at least one datum selected from a group consisting of a set of state transition counts, an amount of time spent by a thread in a subset of thread states, and a set of thread priority raise counts.

41. The multithreaded data processing method of claim 40, further comprising:

transitioning a state of a thread from a ready state to a run state when the thread is scheduled for execution;

transitioning the state of the thread from the run state to an interrupt wait state when the thread receives an interrupt;

transitioning the state of the thread from the run state to a condition wait state when the thread executes a wait condition instruction;

transitioning the state of the thread from the run state to a mutex wait state when the thread executes a lock mutex instruction;

transitioning the state of the thread from the run state to an wait instruction cache state when the thread receives an instruction cache miss signal; and

transitioning the state of the thread from the run state to a wait memory state when the thread receives a data miss signal.

42. The multithreaded data processing method of claim 40, wherein the set of multithreading system call machine code instructions includes a set of mutex locking instructions.

43. The multithreaded data processing method of claim 42, wherein the set of mutex locking instructions comprises a committed lock mutex instruction.

44. The multithreaded data processing method of claim 43, wherein executing the committed lock mutex instruction comprises checking a mutex register to determine whether a mutex identified by the committed lock mutex instruction is locked by a thread executing the committed lock mutex instruction.

45. The multithreaded data processing method of claim 44, wherein executing the committed lock mutex instruction further comprises:

when the mutex identified by the committed lock mutex instruction is not locked by a thread executing the committed lock mutex instruction, checking a thread priority register to compare a priority of the thread executing the committed lock mutex instruction to a priority of a thread holding a lock of the mutex identified by the committed lock mutex instruction; and

when the priority of the thread executing the committed lock mutex instruction is higher than the priority of the thread holding the lock, increasing the priority of the thread holding the lock to at least the priority of the thread executing the committed lock mutex instruction.

46. The multithreaded data processing method of claim 43, wherein the set of mutex locking instructions further comprises a test mutex instruction.

47. The multithreaded data processing method of claim 46, wherein executing the test mutex instruction comprises checking a mutex register to determine whether a mutex identified by the test mutex instruction is locked by a thread executing the test mutex instruction.

48. The multithreaded data processing method of claim 46, wherein the set of mutex locking instructions further comprises an unlock mutex instruction.

49. The multithreaded data processing method of claim 42, wherein the set of mutex locking instructions comprises an unlock mutex instruction, and wherein executing the unlock mutex instruction comprises checking a mutex register to determine whether a mutex identified by the unlock mutex instruction is locked by a thread executing the unlock mutex instruction.

50. The multithreaded data processing method of claim 49, wherein executing the unlock mutex instruction further comprises:

determining whether a set of threads other than the thread executing the unlock mutex instruction are waiting for the mutex identified by the unlock mutex instruction; and

when the set of threads other than the thread executing the unlock mutex instruction are waiting for the mutex identified by the unlock mutex instruction, selecting a highest-priority thread from the set of threads other than the thread executing the unlock mutex instruction, and setting a priority of the highest-priority thread at least as high as a priority of the thread executing the unlock mutex instruction.

51. The multithreaded data processing method of claim 50, wherein executing the unlock mutex instruction further comprises:

when the set of threads other than the thread executing the unlock mutex instruction are waiting for the mutex identified by the unlock mutex instruction, determining a highest priority among a set of threads waiting for any mutex held by the thread executing the unlock mutex instruction; and

setting the priority of the thread executing the unlock mutex instruction at least as high as the highest priority among the set of threads waiting for any mutex held by the thread executing the unlock mutex instruction.

52. The multithreaded data processing method of claim 40, wherein the set of multithreading system call machine code instructions includes a wait condition instruction.

53. The multithreaded data processing method of claim 52, wherein executing the wait condition instruction comprises checking a mutex register to determine whether a mutex identified by the wait condition instruction is locked by a thread executing the wait condition instruction.

54. The multithreaded data processing method of claim 52, wherein executing the wait condition instruction comprises transitioning a state of a thread executing the wait condition instruction from a run state to a condition wait state.

55. The multithreaded data processing method of claim 40, wherein the set of multithreading system call machine code instructions includes a condition signal instruction.

56. The multithreaded data processing method of claim 55, wherein executing the condition signal instruction comprises transitioning a state of a thread waiting for a condition signal from a condition wait state to a ready state.

57. The multithreaded data processing method of claim 40, further comprising scheduling the plurality of threads for execution according to the plurality of thread states and a corresponding plurality of thread priorities.

58. The multithreaded data processing method of claim 40, wherein the thread profiling data includes the set of state transition counts.

59. The multithreaded data processing method of claim 40, wherein the thread profiling data includes the amount of time spent by the thread in the subset of thread states.

60. The multithreaded data processing method of claim 40, wherein the thread profiling data includes the set of thread priority raise counts.

61. The multithreaded data processing method of claim 40, wherein the thread profiling data includes a set of wait state counts.

62. The multithreaded data processing method of claim 40 further comprising:

collecting run profiling data for the plurality of threads using a set of thread run profiling units; and

collecting wait profiling data for the plurality of threads using a set of thread wait profiling units.

63. The multithreaded data processing method of claim 40, further comprising storing the thread profiling data in a set of thread profiling registers.

64. The multithreaded data processing method of claim 40, further comprising storing a thread hardware execution mask corresponding to the set of multithreading system call machine code instructions in a thread hardware execution mask register, the thread hardware execution mask identifying a subset of multithreading system call instructions to be executed in hardware by the thread instructions execution logic, and a subset of multithreading system call instructions to be executed in software by a system thread.

65. The multithreaded data processing method of claim 40, further comprising fetching a set of machine-code instructions for the plurality of threads, the set of machine-code instructions including a set of arithmetic and logical instructions, and the set of multithreading system call instructions.

66. The multithread data processing method of claim 65, wherein the set of instructions includes a set of conditional jump instructions, wherein at least one conditional jump instruction immediately follows and is conditioned on an outcome of a multithreading system call instruction.

67. The multithreaded data processing method of claim 40, further comprising storing a set of flags reflecting an outcome of an execution of a latest multithreading system call machine code instruction in a set of flag registers.

68. The multithreading data processing method of claim 67, wherein the set of flags comprise at least one condition flag defining a condition for a conditional jump instruction immediately following the latest multithreading system call machine code instruction.

69. A multithreaded microcontroller comprising:

an instruction fetching unit configured to receive a set of machine-code instructions for a plurality of threads, the set of instructions including a set of arithmetic and logical instructions, and a set of multithreading system call instructions;

an arithmetic logic unit connected to the instruction fetching unit and configured to receive and execute the set of arithmetic and logical instructions; and

a hardware thread controller connected to the instruction fetching unit and the arithmetic logic unit, configured to receive and execute the set of multithreading system call instructions, wherein the thread controller comprises a hardware thread profiler the thread profiler configured to collect thread profiling data for the plurality of threads, the thread profiling data comprising at least one datum selected from a group consisting of a set of state transition counts, an amount of time spent by a thread in a subset of thread states, and a set of thread priority raise counts.

70. The multithreaded microcontroller of claim 69, wherein the set of multithreading system calls comprises a mutex locking instruction, and the thread control logic comprises mutex locking execution logic configured to execute the mutex locking instruction.

71. The multithreaded microcontroller of claim 70, wherein the mutex locking instruction is a committed lock mutex instruction.

72. The multithreaded microcontroller of claim 70, wherein the mutex locking instruction is a test mutex instruction.

73. The multithreaded microcontroller of claim 70, wherein the mutex locking instruction is an unlock mutex instruction.

74. The multithreaded microcontroller of claim 69, wherein the set of multithreading system calls comprises a wait condition instruction, and the thread control logic comprises wait condition execution logic configured to execute the wait condition instruction.

75. The multithreaded microcontroller of claim 69, wherein the set of multithreading system calls comprises a condition signal instruction, and the thread control logic comprises condition signal execution logic configured to execute the condition signal instruction.

76. The multithreaded microcontroller of claim 69, wherein the thread controller comprises thread state transition logic configured to control a set of thread state transitions.

77. The multithreaded microcontroller of claim 69, wherein the thread controller comprises thread scheduling logic configured to schedule a plurality of threads according to the thread states and a corresponding plurality of thread priorities.

78. The multithreaded microcontroller of claim 69, wherein the thread profiling data includes the set of state transition counts.

79. The multithreaded microcontroller of claim 69, wherein the thread profiling data includes the amount of time spent by a thread in a subset of thread states.

80. The multithreaded microcontroller of claim 69, wherein the thread profiling data includes a set of thread priority raise counts.

81. The multithreaded microcontroller of claim 69, wherein the thread profiling data includes a set of wait state counts.

82. A data processing apparatus comprising:

a plurality of special-purpose hardware cores integrated on a chip; and

a multithreaded microcontroller integrated on the chip and connected to the plurality of cores, the microcontroller controlling a plurality of threads including a first thread communicating with a first core and a second thread communicating with a second core, the multithreaded microcontroller including

a set of special-purpose multithreading registers including a set of thread state registers storing a plurality of thread states for the plurality of threads; and

thread control logic connected to the set of multithreading registers, comprising;

thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads;

thread instructions execution logic connected to the thread state transition logic and configured to execute a set of multithreading system call machine code instructions; and

a hardware thread profiler connected to the set of multithreading registers, the thread profiler comprising thread profiling logic configured to collect thread profiling data for the plurality of threads, the thread profiling data comprising at least one datum selected from a group consisting of a set of state transition counts, an amount of time spent by a thread subset of thread states, and a set of thread priority raise counts.

83. The data processing apparatus of claim 82, wherein:

the plurality of cores includes at least one video coding core and at least one audio coding core;

the plurality of threads including a video coding thread communicating with the video coding core and an audio coding thread communicating with the audio coding core.

84. A data processing apparatus comprising:

a multithreaded instruction execution unit configured to run a plurality of threads; and

a hardware thread profiler connected to the multithreaded instruction execution unit, the thread profiler comprising;

thread profiling logic configured to collect thread profiling data for the plurality of threads, the thread profiling data comprising at least one datum selected from a thread state transition count a time period spent by a thread in a set of thread states, and a set of priority raise counts; and

a set of thread profiling registers connected to the thread profiling logic and storing the thread profiling data.

85. The data processing apparatus of claim 84, wherein the thread profiling data includes a set of state transition counts.

86. The data processing apparatus of claim 84, wherein the thread profiling data includes the amount of time spent by the thread in the set of thread states.

87. The data processing apparatus of claim 84, wherein the thread profiling data includes the set of thread priority raise counts.

88. The data processing apparatus of claim 84, wherein the thread profiling data includes a set of wait state counts.

89. The data processing apparatus of claim 84, wherein the thread profiler comprises:

a set of thread run profiling units configured to collect run profiling data for the plurality of threads; and

a set of thread wait profiling units configured to collect wait profiling data for the plurality of threads.

90. The data processing apparatus of claim 89, wherein the set of thread profiling registers includes:

a set of run profiling registers storing a set of thread run profiling data for the plurality of threads; and

a set of wait profiling registers storing a set of thread wait profiling data for the plurality of threads.

91. A data processing apparatus comprising:

a set of special-purpose multithreading registers including

a set of thread state registers storing a plurality of thread states for a corresponding plurality of threads;

a set of mutex registers storing a plurality of mutex states for a corresponding plurality of mutexes; and

a set of condition variable registers storing a plurality of condition variable states for a corresponding plurality of condition variables;

thread control logic connected to the set of multithreading registers, comprising;

thread state transition logic connected to the set of thread state registers and configured to control thread state transitions for the plurality of threads; and

thread instructions execution logic connected to the thread state transition logic and configured to execute a set of multithreading system call machine code instructions, the thread instructions execution logic comprising mutex locking logic connected to the set of mutex registers and configured to execute a set of mutex locking instructions according to the set of mutex states, and

wait condition logic connected to the set of mutex registers configured to execute a wait condition instruction according to the set of mutex states and the set of condition variable states; and

a hardware thread profiler connected to the set of multithreading registers, the thread profiler comprising thread profiling logic configured to collect thread profiling data for the plurality of threads, the thread profiling data comprising at least one datum selected from a group consisting of a set of state transition counts, an amount of time spent by a thread in a subset of thread states, and a set of thread priority raise counts.