Manufacturing method of array substrate and manufacturing method of liquid crystal display device using the same
First Claim
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1. A manufacturing method of an array substrate, comprising the steps of:
- forming, within each pixel, at least a gate bus of a thin film transistor and a plurality of structures, the gate bus and the structures being formed from a metal film formed on the substrate, and the structures being arranged in an irregular pattern;
forming an under layer on the substrate over the thin film transistor and over the plurality of structures to form irregularities, controlled by the plurality of structures, on a surface of the under layer;
forming on the under layer a thin film with irregularities profiling the surface of the under layer;
forming a resist layer on the thin film;
forming a regularly arranged resist pattern by patterning the resist layer;
performing an optical inspection of the resist layer to optically detect a defect in the resist pattern; and
etching the thin film while using the resist pattern as a mask;
wherein the resist pattern is formed without openings within each pixel so that the irregularities of the thin film are not recognized through the resist pattern in the optical inspection.
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Abstract
In the manufacturing method of the array substrate, an under layer having a surface with irregular irregularities is formed on a substrate, a metal film with irregularities profiling the surface of the under layer is formed on the under layer, a colored resist layer is formed on the metal film, the colored resist layer is patterned to form a regularly arranged colored resist pattern, an optical inspection is performed to optically detect a defect of the colored resist pattern, a defect of the colored resist pattern detected by the optical inspection is repaired; and the metal film is etched while using the resist pattern as a mask.
40 Citations
7 Claims
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1. A manufacturing method of an array substrate, comprising the steps of:
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forming, within each pixel, at least a gate bus of a thin film transistor and a plurality of structures, the gate bus and the structures being formed from a metal film formed on the substrate, and the structures being arranged in an irregular pattern; forming an under layer on the substrate over the thin film transistor and over the plurality of structures to form irregularities, controlled by the plurality of structures, on a surface of the under layer; forming on the under layer a thin film with irregularities profiling the surface of the under layer; forming a resist layer on the thin film; forming a regularly arranged resist pattern by patterning the resist layer; performing an optical inspection of the resist layer to optically detect a defect in the resist pattern; and etching the thin film while using the resist pattern as a mask; wherein the resist pattern is formed without openings within each pixel so that the irregularities of the thin film are not recognized through the resist pattern in the optical inspection. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Current AssigneeSharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
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Original AssigneeSharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
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InventorsSugine, Mitsuaki
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Primary Examiner(s)Coleman; W. David
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Assistant Examiner(s)Malek; Maliheh
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Application NumberUS11/055,696Publication NumberTime in Patent Office2,000 DaysField of Search438/8, 438/12, 438/149, 438151-159, 438 22- 47, 438/163, 438/48, 349/30, 349 43- 44, 349/67, 349112-114, 257/59, 257/72, 257/98, 257/432, 257/E21.53, 257E51005-E51006US Class Current438/30CPC Class CodesG02F 1/133553 Reflecting elements associa...G02F 1/136259 Repairing; DefectsH01L 22/24 Optical enhancement of defe...H01L 27/14692 Thin film technologies, e.g...
