Method for sealing and backside releasing of microelectromechanical systems

• US 7,767,484 B2
• Filed: 05/30/2007
• Issued: 08/03/2010
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Ayazi, Farrokh
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): Ligai; Maria
• Application Number:
  US11/807,848
• Publication Number:
  US 20070281381A1
• Time in Patent Office: 1,161 Days
• Field of Search: 257/E29.324, 257/E21.613, 438/50, 438/52, 438/53, 438/456
• US Class Current: 438/52
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00285 using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters
• CPC Class Codes: B81C 1/00476 removing a sacrificial layer B81C1/00912 takes precedence

Abstract

Disclosed are methods for fabricating encapsulated microelectromechanical systems (MEMS) devices. A MEMS device fabricated on a CMOS wafer is encapsulated using an etch resistant thin film layer prior to the release of the MEMS device. Once CMOS processing is completed, the wafer is etched to release the MEMS device. If the MEMS is fabricated on a silicon-on-insulator (SOI) wafer, the buried oxide of the SOI wafer acts as an etch stop for the etching. A sacrificial layer(s) is accessed and removed from the back side of the wafer, while the front side of the wafer is protected by a masking layer. The MEMS device is released without having any detrimental effects on CMOS components. If desired, the wafer can be mounted on another substrate to provide hermetic or semi-hermetic sealing of the device.

Claims

1. A method for encapsulating and integrating nano- and/or micro-electromechanical systems (MEMS) comprising:

providing a semiconductor-on-insulator substrate comprising a handle layer, a device layer, and an insulating layer disposed between the handle and device layers;

fabricating a transistor-based circuit in the device layer;

fabricating a MEMS device in the device layer;

forming an etch resistant layer over the MEMS device and into the device layer;

forming a silicon dioxide sacrificial layer;

etching the handle layer beneath the MEMS device using the insulating layer as an etch stop; and

releasing the MEMS device from the device layer through the backside of the substrate using an etchant, wherein the etch-resistant layer is resistant to the etchant and the etch-resistant layer protects the transistor-based circuit from the etchant,

wherein releasing the MEMS device comprises removing the silicon dioxide sacrificial layer in a hydrofluoric acid.

2. The method recited in claim 1 wherein the transistor-based circuit is a CMOS circuit.

3. The method recited in claim 1 further comprising:

attaching the handle layer to another substrate, thereby forming an enclosed sealed cavity in which the MEMS device is disposed.

4. The method recited in claim 3 further comprising:

disposing a getter material in the enclosed sealed cavity.

5. The method recited in claim 1 wherein the device layer of the substrate is a semiconductor selected from a group including single crystalline silicon, poly-crystalline silicon, silicon carbide, diamond, gallium nitride and gallium arsenide.

6. The method recited in claim 1 wherein the MEMS device comprises a resonator.

7. The method recited in claim 1 wherein the etch resistant layer comprises a low-pressure chemical vapor deposited (LPCVD) hydrofluoric acid resistant layer.

8. The method recited in claim 1 wherein the etch resistant layer comprises a silicon nitride layer.

9. The method recited in claim 1 wherein the etch resistant layer comprises a polysilicon layer.

10. The method recited in claim 1 wherein the semiconductor-on-insulator substrate comprises a silicon-on-silicon dioxide substrate.

11. The method of claim 1, further comprising:

covering the transistor-based circuit and the MEMS device with a masking layer, wherein the masking layer is resistant to the etchant and further protects the transistor-based circuit from the etchant.

12. The method of claim 1, wherein the etch resistant layer extends over the MEMS device on a frontside of the substrate, wherein the etch resistant layer extends through the device layer.

13. The method of claim 12, wherein the etch resistant layer contacts the handle layer.

14. The method of claim 1, wherein the etch resistant layer is spaced apart from a movable portion of the MEMS device.

15. The method of claim 1, further comprising:

forming, in the device layer, a sacrificial layer that immobilizes the MEMS device,

wherein releasing the MEMS device comprises removing the sacrificial layer through the backside of the substrate using the etchant.

16. A method for encapsulating and integrating nano and/or microelectromechanical systems (MEMS) comprising:

providing a semiconductor-on-insulator substrate comprising a handle layer, a device layer, and an insulating layer disposed between the handle and device layers;

fabricating a transistor-based circuit in the device layer;

covering the transistor-based circuit with a masking layer;

fabricating a MEMS device in the handle layer;

fabricating, in the handle layer, a sacrificial layer that immobilizes the MEMS device; and

releasing the MEMS device using an etchant to remove the sacrificial layer, wherein the masking layer is resistant to the etchant and the masking layer protects the transistor-based circuit from the etchant.

17. The method recited in claim 16 wherein the transistor based circuit is a CMOS circuit.

18. The method recited in claim 17 wherein the MEMS device comprises a resonator.

19. The method recited in claim 16 wherein the device layer of the substrate is a semiconductor selected from a group including single crystalline silicon, poly-crystalline silicon, silicon carbide, diamond, gallium nitride and gallium arsenide.

20. The method recited in claim 19 further comprising:

attaching the handle layer to another substrate, thereby forming an enclosed sealed cavity in which the MEMS device is disposed.

21. The method recited in claim 20 further comprising:

disposing a getter material in the enclosed sealed cavity.

22. The method recited in claim 16 wherein releasing the MEMS device from the substrate comprises removing a silicon dioxide sacrificial layer in a hydrofluoric acid.

23. A method for encapsulating and integrating nano- and/or micro-electromechanical systems (MEMS) comprising:

providing a semiconductor-on-insulator substrate comprising a handle layer, a device layer, and an insulating layer disposed between the handle and device layers;

fabricating a transistor-based circuit in the device layer;

fabricating a MEMS device in the device layer;

covering the MEMS device with an etch resistant layer;

etching the handle layer beneath the MEMS device using the insulating layer as an etch stop; and

releasing the MEMS device from the device layer through the backside of the substrate using an etchant, wherein the etch-resistant layer is resistant to the etchant and the etch-resistant layer protects the transistor-based circuit from the etchant,

wherein the etch resistant layer extends over the MEMS device on a frontside of the substrate, wherein the etch resistant layer extends through the device layer and contacts the handle layer.

24. The method of claim 23, further comprising:

attaching the handle layer to another substrate, thereby forming an enclosed sealed cavity in which the MEMS device is disposed.

25. The method recited in claim 23, wherein releasing the MEMS device comprises removing a sacrificial layer from the device layer using the etchant.

26. The method of claim 25, wherein the sacrificial layer comprises silicon dioxide and the etchant comprises hydrofluoric acid.

27. The method of claim 23, further comprising:

covering the transistor-based circuit and the MEMS device with an unpatterned masking layer,

wherein the unpatterned masking layer is resistant to the etchant and protects the transistor-based circuit from the etchant.

28. The method of claim 23, wherein the etch resistant layer comprises a material selected from the group consisting of silicon nitride and polysilicon.

29. The method of claim 23, wherein the etch resistant layer is formed by low-pressure chemical vapor deposition.