Method and structure for forming a shielded gate field effect transistor

• US 7,767,524 B2
• Filed: 10/20/2009
• Issued: 08/03/2010
• Est. Priority Date: 06/10/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok, Yilmaz, Hamza, Calafut, Daniel, Kraft, Nathan, Sapp, Steven
• Primary Examiner(s): Pham; Thanh V
• Application Number:
  US12/582,487
• Publication Number:
  US 20100038708A1
• Time in Patent Office: 287 Days
• Field of Search: 438/259, 438/270, 257/330, 257/332, 257/E29.201
• US Class Current: 438/259
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

Claims

1. A method of forming a charge balance MOSFET comprising:

providing a substrate of a first conductivity type with an epitaxial layer of the first conductivity type extending over the substrate;

forming a gate trench extending through the epitaxial layer and terminating within the substrate;

forming a shield dielectric lining sidewalls and bottom surface of the gate trench;

forming a shield electrode in the gate trench;

forming a gate dielectric layer along upper sidewalls of the gate trench;

forming a gate electrode in the gate trench, the gate electrode being over but insulated from the shield electrode;

forming a deep dimple extending through the epitaxial layer and terminating within the substrate, the deep dimple being laterally spaced from the gate trench; and

filling the deep dimple with silicon material of the second conductivity type.

2. The method of claim 1 further comprising:

forming a body region of the second conductivity type in the epitaxial layer;

forming source regions of the first conductivity type in the body region, the source regions flanking the gate trench;

forming heavy body regions of the second conductivity type in the body region; and

forming a source interconnect layer contacting the source regions and the heavy body regions.

3. A MOSFET comprising:

a substrate of a first conductivity type;

an epitaxial layer of the first conductivity type over the substrate;

a gate trench extending through the epitaxial layer and terminating within the substrate;

a shield dielectric lining sidewalls and bottom surface of the gate trench;

a shield electrode in a lower portion of the gate trench;

a gate dielectric layer along upper sidewalls of the gate trench;

a gate electrode in the gate trench, the gate electrode being over but insulated from the shield electrode; and

a deep dimple extending through the epitaxial layer and terminating within the substrate, the deep dimple being laterally spaced from the gate trench, wherein the deep dimple is filled with silicon material of the second conductivity type.

4. The MOSFET of claim 3 further comprising:

a body region of the second conductivity type in an upper portion of the epitaxial layer;

source regions of the first conductivity type in the body region, the source regions flanking the gate trench; and

heavy body regions of the second conductivity type in the body region.

5. A method of forming a charge balance MOSFET, comprising:

providing a substrate of a first conductivity type;

forming an epitaxial layer of the first conductivity type over the substrate;

forming a plurality of gate trenches extending through the epitaxial layer and terminating within the substrate;

forming a shield dielectric lining sidewalls and bottom surface of each gate trench;

forming a shield electrode in each gate trench;

forming a gate dielectric layer along upper sidewalls of each gate trench;

forming a gate electrode in each gate trench, the gate electrode being over but insulated from the shield electrode; and

performing a plurality of ion implantations of dopants of the second conductivity type into mesa regions between adjacent gate trenches to thereby form a plurality of pillars of second conductivity type extending through the epitaxial layer and terminating within the substrate, each pillar of second conductivity type being located between every two gate trenches.

6. The method of claim 5 further comprising:

forming a body region of the second conductivity type in the epitaxial layer;

forming source regions of the first conductivity type in the body region, the source regions flanking the plurality of gate trenches;

forming heavy body regions of the second conductivity type in the body region; and

forming a source interconnect layer contacting the source regions and the heavy body regions.

7. The method of claim 5 further comprising:

prior to performing the plurality of ion implantations, forming a shallow dimple in a mesa region adjacent the gate trench, wherein the plurality of ion implantations are carried out through the shallow dimple.

8. The method of claim 5 further comprising:

prior to performing the plurality of ion implantations;

forming a body region of the second conductivity type in an upper portion of the epitaxial layer;

forming a silicon region of the first conductivity type in an upper portion of the body region; and

performing a silicon etch to form a shallow dimple extending through the silicon region so as to divide the silicon region into two regions each forming a source region, wherein the plurality of ion implantations are carried out through the shallow dimple.