Method for producing a vertical transistor component

• US 7,767,527 B2
• Filed: 09/30/2005
• Issued: 08/03/2010
• Est. Priority Date: 09/30/2004
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Rieger, Walter, Poelzl, Martin
• Primary Examiner(s): Wilczewski; Mary
• Assistant Examiner(s): Thomas; Toniae M
• Application Number:
  US11/241,867
• Publication Number:
  US 20060097312A1
• Time in Patent Office: 1,768 Days
• Field of Search: 438/212, 438268-270, 438/589, 257/E21.41
• US Class Current: 438/269
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for producing a vertical transistor component includes steps of providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extends as far as the semiconductor substrate and which has opposite sidewalls. The method further includes producing a monocrystalline semiconductor layer on at least one of the sidewalls of the trench, producing an electrode insulated from the monocrystalline semiconductor layer on the at least one sidewall of the trench and the semiconductor substrate.

Claims

1. A method for producing a vertical transistor component, comprising:

a) providing a semiconductor substrate,

b) providing an auxiliary layer on the semiconductor substrate,

c) patterning the auxiliary layer such that at least a first trench is produced that extends as far as a surface of the semiconductor substrate, the first trench having opposite sidewalls,

d) producing a monocrystalline semiconductor layer on at least one of the sidewalls of the first trench, and

e) producing an electrode insulated from the monocrystalline semiconductor layer and the semiconductor substrate,

f) removing the auxiliary layer, thereby forming a second trench that extends to the substrate;

g) introducing dopants of a conduction type that is complementary to the conduction type of the semiconductor substrate in the semiconductor substrate at the bottom of the second trench, thereby forming a further semiconductor zone that forms a pn-junction with the semiconductor substrate;

h) forming an electrode in the second trench that contacts the further semiconductor zone.

2. The method according to claim 1, wherein step d) further comprises:

applying an amorphous semiconductor layer, recrystallizing the amorphous semiconductor layer by carrying out a thermal process.

3. The method according to claim 2, wherein the amorphous semiconductor layer is doped in situ with dopant atoms.

4. The method according to claim 1, further comprising etching back the auxiliary layer after step d), such that the monocrystalline semiconductor layer extends above the auxiliary layer on a side remote from the substrate.

5. The method according to claim 1, wherein step e) further comprises:

providing an insulation layer at least on that side of the monocrystalline semiconductor layer which faces the trench and on regions of the semiconductor substrate which are uncovered within the first trench, and filling the first trench with an electrode material.

6. The method according to claim 5, further comprising applying a protective layer, in least in sections, on a side of the electrode remote from the substrate.

7. The method according to claim 6, further comprising removing the protective layer at least in sections above the electrode such that the electrode is contact-connectable in self-aligning fashion.

8. The method according to claim 1, wherein the first trench has at least one section in which a widened section of the electrode is formed, the electrode being contact-connectable at the widened section.

9. The method according to claim 1, wherein the semiconductor substrate is doped with dopant atoms of a first conduction type, and further comprising, in the monocrystalline semiconductor layer:

producing a first semiconductor zone of the first conduction type on a side of the first semiconductor zone remote from the substrate, and producing a complementarily doped second semiconductor zone subsequent to said first semiconductor zone.

10. The method according to claim 9, wherein the first semiconductor zone is produced by implantation of dopant atoms and subsequent activation of the dopant atoms.

11. The method according to claim 9, wherein the second semiconductor zone is produced by implantation of dopant atoms and subsequent activation of the dopant atoms.

12. The method according to claim 9, wherein the second semiconductor zone is formed by a section having a basic doping of the monocrystalline semiconductor layer.

13. The method according to claim 9, wherein a third semiconductor zone of the first conduction type as the semiconductor substrate is produced in the monocrystalline semiconductor layer between the semiconductor substrate and the second semiconductor zone.

14. The method according to claim 13, wherein the third semiconductor zone is produced using a thermal step, the thermal step having a temperature and a duration chosen such that dopant atoms diffuse from the semiconductor substrate into the monocrystalline semiconductor layer.

15. The method according to claim 1, wherein the monocrystalline semiconductor layer is doped with dopant atoms of a same conduction type as the semiconductor substrate.

16. The method according to claim 1, further comprising introducing dopants into a section of the semiconductor substrate which extends into said semiconductor substrate and which is arranged on a side of the monocrystalline semiconductor layer that is remote from the electrode.

17. A method for producing a vertical transistor component, comprising:

a) providing a semiconductor substrate,

b) applying an auxiliary layer to the semiconductor substrate,

c) patterning the auxiliary layer to produce at least a first trench which extends to the semiconductor substrate,

d) producing a monocrystalline semiconductor zone in the first trench,

e) removing the auxiliary layer at least in sections, the removal of the auxiliary layer such that the monocrystalline semiconductor zone is in pillar form,

f) producing an electrode insulated from the monocrystalline semiconductor zone and the semiconductor substrate, and further producing an insulation layer on sidewalls of the monocrystalline semiconductor zone, and on the semiconductor substrate, wherein producing the electrode comprises depositing an electrode material,

wherein applying the auxiliary layer comprises providing an embedded electrode layer in the auxiliary layer in a manner spaced apart from the semiconductor substrate, wherein patterning the auxiliary layer comprises patterning the electrode layer together with the auxiliary layer, wherein removing the auxiliary layer comprises removing the auxiliary layer before the production of the electrode only in regions above the electrode layer, and

g) providing an insulation layer on the electrode layer before step f).

18. The method according to claim 17, wherein the monocrystalline semiconductor zone is doped complementarily with respect to the semiconductor substrate, and further comprising:

producing a first semiconductor zone of a same conduction type as the semiconductor substrate at an end of the monocrystalline semiconductor zone which is remote from the semiconductor substrate.

19. The method according to claim 18, further comprising producing, in the monocrystalline semiconductor zone adjacent to the semiconductor substrate, a second semiconductor zone of a same conduction type as the semiconductor substrate.

20. The method according to claim 19, wherein the second semiconductor zone is produced using a thermal step, the thermal step having a temperature and duration chosen such that dopant atoms diffuse from the semiconductor substrate into the monocrystalline semiconductor zone.

21. The method according to claim 17, wherein producing the first semiconductor zone further comprises:

producing a dopant zone on the monocrystalline semiconductor zone, and indiffusing dopant atoms from the dopant zone into the monocrystalline semiconductor zone.

22. The method according to claim 21, wherein the auxiliary layer extends above the monocrystalline semiconductor zone, and wherein the dopant zone is produced on the monocrystalline semiconductor zone in a region proximate to a sidewall of the auxiliary layer.