Semiconductor component and method of manufacture

• US 7,767,529 B2
• Filed: 04/20/2007
• Issued: 08/03/2010
• Est. Priority Date: 04/20/2007
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Venkatraman, Prasad, Grivna, Gordon M., Robb, Francine Y., Chang, George, Casteel, Carroll
• Primary Examiner(s): Blum; David S
• Application Number:
  US11/737,923
• Publication Number:
  US 20080258210A1
• Time in Patent Office: 1,201 Days
• Field of Search: 438/426, 438/270, 438/430, 257/E21.41, 257/E29.257
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having a major surface;

forming one or more trenches in the semiconductor material; and

forming a field oxide from a peripheral region of the semiconductor material, wherein the one or more trenches extends directly under the field oxide.

2. The method of claim 1, wherein providing the semiconductor material includes providing a substrate having an epitaxial layer disposed thereon.

3. The method of claim 1, further including forming polysilicon in the one or more trenches and polysilicon over a portion of the field oxide.

4. The method of claim 3, further including forming a first doped region of a first conductivity type in a first portion of the semiconductor material and a second doped region of a second conductivity type in a second portion of the semiconductor material.

5. The method of claim 4, wherein forming the second doped region comprises:

forming a layer of dielectric material over the polysilicon in the one or more trenches and over the polysilicon that is over the field oxide;

removing a portion of the layer of dielectric material that is between the field oxide and a first trench of the one or more trenches; and

doping the second portion of the semiconductor material to form the second doped region.

6. The method of claim 5, wherein removing the portion of the layer of dielectric material that is between the field oxide and the first trench includes removing a portion of the field oxide.

7. The method of claim 3, further including:

forming a first doped region of a first conductivity type in the semiconductor material before forming the one or more trenches, wherein the one or more trenches extend further from the major surface into the semiconductor material than the first doped region;

forming a second doped region by;

forming a layer of dielectric material over the polysilicon in the one or more trenches and over the polysilicon that is over the field oxide;

removing a portion of the field oxide and a portion of the layer of dielectric material that is between the field oxide and a first trench of the one or more trenches to expose a first portion of the first doped region;

etching through the exposed first portion of the first doped region to expose a second portion of the semiconductor material; and

doping the second portion of the semiconductor material with an impurity material of a second conductivity type.

8. The method of claim 7, wherein the first conductivity type is N conductivity type and the second conductivity type is P conductivity type.

9. The method of claim 7, further including forming a metal contact to the first and second doped regions and to the second surface of the semiconductor material.

10. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having first and second major surfaces, the semiconductor material comprising an epitaxial layer disposed on a semiconductor substrate and having an active area and a peripheral area;

forming a plurality of trench structures in the semiconductor material, wherein the plurality of trench structures extend vertically from the first major surface into the epitaxial layer and laterally from the active area to the peripheral area; and

forming field oxide from the peripheral area, wherein a portion of the plurality of trenches extends directly under the field oxide.

11. The method of claim 10, wherein providing the semiconductor material includes providing a layer of impurity material of a first conductivity type extending from the first major surface into the semiconductor material a first distance, and further including:

forming a layer of polysilicon over the active and the peripheral areas;

patterning the layer of polysilicon, leaving a first portion of the layer of polysilicon over a first portion of the field oxide and a second portion of the layer of polysilicon over at least one of the plurality of trench structures;

forming a layer of dielectric material over the first portion of the layer of polysilicon and over the second portion of the layer of polysilicon;

forming a masking structure from the layer of dielectric material, wherein a first portion of the layer of dielectric material remains over the first portion of the layer of polysilicon and a second portion of the layer of dielectric material remains over the second portion of the layer of polysilicon, and wherein a second portion of the layer of dielectric material is exposed;

removing the second portion of the layer of dielectric material to expose a portion of the field oxide;

removing the exposed portion of the field oxide to expose a portion of the layer of impurity material; and

forming a trench in the layer of semiconductor material, the trench having a floor and a sidewall and extending from the major surface of the exposed portion of the layer of impurity material into the semiconductor material a second distance, wherein the floor exposes a second portion of the semiconductor material and wherein the second distance is greater than the first distance and the sidewall exposes a portion of the layer of impurity material of the first conductivity type.

12. The method of claim 11, further including forming a doped region of a second conductivity type in the second portion of the semiconductor material.

13. The method of claim 12, further including forming a first conductor in contact with the second doped region and the sidewall of the trench and a second conductor in contact with the second major surface.

14. The method of claim 10, wherein providing the semiconductor material includes providing a layer of impurity material of a first conductivity type extending from the first major surface into the semiconductor material a first distance, and further including:

forming a layer of polysilicon over the active and the peripheral areas;

patterning the layer of polysilicon, leaving a first portion of the layer of polysilicon over a first portion of the field oxide layer and a second portion of the layer of polysilicon in a first trench of the plurality of trenches, and a third portion of the layer of polysilicon in a third trench of the plurality of trenches;

forming a layer of dielectric material over at least the first, second, and third portions of the layer of polysilicon;

forming a masking structure from the layer of dielectric material, wherein a first portion of the layer of dielectric material remains over the first portion of the layer of polysilicon and second and third portions of the layer of dielectric material remain over the second and third portions of the layer of polysilicon, and wherein a second portion of the layer of dielectric material is exposed;

removing the second portion of the layer of dielectric material to expose the field oxide between the first and second trenches;

removing the exposed portion of the field oxide to expose a portion of the layer of impurity material; and

forming a trench in the layer of semiconductor material between the first and second trenches, the trench having a floor, first and second sidewalls, and extending from the major surface of the exposed portion of the layer of impurity material into the semiconductor material a second distance, wherein the floor exposes a second portion of the semiconductor material and wherein the second distance is greater than the first distance and the first and second sidewalls expose a portion of the layer of impurity material of the first conductivity type.

15. The method of claim 14, further including forming a doped region of a second conductivity type in the second portion of the semiconductor material.