Field effect structure and method including spacer shaped metal gate with asymmetric source and drain regions
First Claim
1. A semiconductor structure comprising:
- a semiconductor substrate that includes a channel region;
a plurality of source regions and drain regions located within the semiconductor substrate and separated by the channel region;
a metal gate that has a spacer shape located over the channel region, where the plurality of source regions and drain regions is asymmetric with respect to the metal gate; and
a spacer located on opposite sidewalls of said metal gate, wherein the spacer on one sidewall has a different height than the spacer on the opposing sidewall.
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Accused Products
Abstract
A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device, such as a field effect transistor, that includes a spacer shaped metal gate located over a channel within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. Within the semiconductor structure, the plurality of source and drain regions is asymmetric with respect to the spacer shaped metal gate. The particular semiconductor structure may be fabricated using a self aligned dummy gate method that uses a portion of a spacer as a self alignment feature when forming the spacer shaped metal gate, which may have a sub-lithographic linewidth.
16 Citations
20 Claims
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1. A semiconductor structure comprising:
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a semiconductor substrate that includes a channel region; a plurality of source regions and drain regions located within the semiconductor substrate and separated by the channel region; a metal gate that has a spacer shape located over the channel region, where the plurality of source regions and drain regions is asymmetric with respect to the metal gate; and a spacer located on opposite sidewalls of said metal gate, wherein the spacer on one sidewall has a different height than the spacer on the opposing sidewall. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor structure comprising:
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a semiconductor substrate that includes a channel region; a plurality of source regions and drain regions located within the semiconductor substrate and separated by the channel region; a metal gate that has a spacer shape located over the channel region; a gate dielectric located interposed between the metal gate and the channel; and a spacer located adjacent opposite sidewalls of the metal gate and located on an upper surface of the gate dielectric, wherein the spacer on one sidewall has a different height than the spacer on the opposing sidewall and, where the plurality of source regions and drain regions is asymmetric with respect to the metal gate. - View Dependent Claims (13, 14, 15)
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16. A method for fabricating a semiconductor structure comprising:
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forming a dummy gate over a semiconductor substrate; forming a first spacer adjacent the dummy gate; forming a plurality of source regions and drain regions into the semiconductor substrate that are separated by a channel within the semiconductor substrate while using, at least in part, the gate and the first spacer as a mask; stripping a portion of the first spacer, and all of the dummy gate, from over the semiconductor substrate to leave a remaining portion of the first spacer over the semiconductor substrate; forming a spacer shaped metal gate over the channel and asymmetric with respect to the plurality of source regions and drain regions while using the remaining portion of the first spacer as a self-alignment feature; and forming a second spacer on an opposing sidewall of said spacer shaped metal gate not including said first spacer, wherein said first and second spacer have different spacer heights. - View Dependent Claims (17, 18, 19, 20)
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Specification