DRAM including a vertical surround gate transistor

• US 7,768,051 B2
• Filed: 07/25/2005
• Issued: 08/03/2010
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Abbott, Todd R.
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Patton; Paul E
• Application Number:
  US11/188,507
• Publication Number:
  US 20070090363A1
• Time in Patent Office: 1,835 Days
• Field of Search: 257/67, 257/296, 257/298, 257/302, 257/329, 257/908, 257/E27.984, 257/E27.088, 257/E29.13, 257/E29.131, 438/268, 438/270
• US Class Current: 257/296
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

Claims

1. A DRAM memory device comprising:

a vertical transistor comprising a first source/drain arranged at an upper end of the vertical transistor, a second source/drain arranged at a lower end of the vertical transistor, a surround gate, and a channel region, wherein the surround gate and the channel are arranged generally between the upper and lower ends of the vertical transistor;

a bit line electrically coupled to the second source/drain of the vertical transistor, the bit line arranged at the upper end of the vertical transistor and wherein the gate comprises a word line of the memory device;

a vertically extending conductive structure connected to the bit line and to a contact arranged at the lower end of the vertical transistor; and

a capacitor electrically coupled to the first source/drain, wherein the capacitor is also arranged adjacent the upper end of the transistor.

2. The DRAM of claim 1, wherein at least a portion of the second source/drain is silicided to form a bit line contact.

3. The DRAM of claim 1, wherein the word line of the vertical transistor is silicided.

4. The DRAM of claim 1, wherein the DRAM has a feature size of less than about 4F².

5. The DRAM of claim 1, wherein the surround gate comprises a silicided gate and a polysilicon gate.

6. The DRAM of claim 1, wherein the bit line comprises material selected from the group comprising:

Tungsten, Aluminum, and Copper.

7. A DRAM comprising a 4F² vertical surround gate transistor, the DRAM further comprising a capacitor and a bit line, wherein both the capacitor and the bit line are arranged adjacent an upper end of the vertical transistor and wherein the bit line is connected to a first source/drain of the transistor arranged at a lower end of the transistor and wherein the capacitor is connected to a second source/drain of the transistor arranged at an upper end of the transistor.

8. The DRAM of claim 7, wherein the vertical surround gate transistor comprises a silicided gate and a polysilicon gate.

9. A method of manufacturing a DRAM memory device, the method comprising:

forming a vertical surround gate transistor having a feature size of less than about 4F², the vertical surround gate transistor comprising a first source/drain arranged at an upper end of the vertical transistor, a second source/drain formed generally at a lower end of the vertical transistor, a surround gate, and a channel region, wherein the gate comprises a word line of the memory device;

forming a bit line so that the bit line is electrically coupled to the second source/drain of the vertical transistor such that the bit line and the first source/drain are both arranged at the upper end of the vertical transistor;

forming a contact such that the contact extends from the bit line arranged at the upper end of the vertical transistor to the second source/drain that is arranged adjacent the lower end of the vertical transistor; and

forming a capacitor so that the capacitor is electrically coupled to the first source/drain and such that the capacitor is also arranged adjacent the upper end of the transistor.

10. The method of claim 9, further comprising siliciding the word line.

11. The method of claim 9, further comprising siliciding the bit line.

12. A DRAM memory device comprising:

a vertical transistor comprising a first source/drain arranged at an upper end of the vertical transistor, a second source/drain, a surround gate, and a channel region wherein the second source/drain is arranged adjacent a lower end of the channel region and wherein, at least a portion of the gate is silicided to form a word line contact of the memory device;

a bit line electrically coupled to the second source/drain of the vertical transistor and wherein the bit line is arranged proximal the upper end of the vertical transistor; and

a capacitor electrically coupled to the first source/drain wherein both the first source/drain and the capacitor are arranged proximal the upper end of the vertical transistor.

13. The DRAM of claim 12, wherein the gate comprises a surround gate.

14. A method of forming a memory device having a vertical transistor, the method comprising:

forming a semiconductor substrate comprising a first layer having a first doping type and a second layer above the first layer having a complementary second doping type, a third layer having the first doping type, and a fourth layer having the second doping type;

forming a silicided contact in electrical contact with a first source/drain formed in the second layer such that the first source/drain is arranged proximal the first layer of the substrate and such that the contact extends upwards from the first source/drain to adjacent the fourth layer;

forming a vertical semiconductor pillar comprising portions of at least the third and fourth layers such that at least portions of the fourth layer in the pillar define a second source/drain region arranged at an upper end of the pillar and such that the first source/drain is arranged at a lower end of the pillar and at least portions of the third layer in the pillar define a channel region arranged intermediate the first source/drain and second source/drain;

forming a dielectric layer on exposed portions of the third and fourth layers;

forming a vertically extending polysilicon gate on the dielectric layer, so as to define a gate substantially surrounding at least those portions of the pillar comprising the third layer;

forming a vertically extending silicided gate on the polysilicon gate; and

forming a capacitor in electrical contact with the second source/drain region such that the capacitor is also arranged adjacent the upper end of the pillar.

15. The method of claim 14, wherein the first layer comprises a n-type semiconductor material and the second layer comprises a p-type semiconductor material.

16. The method of claim 14, wherein the first layer comprises a p-type semiconductor material and the second layer comprises a n-type semiconductor material.

17. The method of claim 14, wherein the memory device is DRAM.

18. The method of claim 14, wherein the silicided gate is electrically coupled to a wordline of the memory device.

19. The method of claim 14, wherein the silicided contact is electrically coupled to a bitline of the memory device, wherein the bitline is also arranged adjacent the upper end of the pillar.

20. The method of claim 19, wherein the bitline comprises material selected from the group comprising:

Tungsten, Aluminum, and Copper.

21. A vertical memory cell comprising:

a source region;

a drain region;

a polysilicon surround gate extending generally vertically between the source region and drain region;

a channel region extending generally vertically between the source region and the drain region; and

a vertically extending silicided surround gate contact arranged adjacent the polysilicon surround gate wherein the polysilicon surround gate and the silicided surround gate contact extend along a vertical length of the channel region.