Isolated-nitride-region non-volatile memory cell and fabrication method
First Claim
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1. An isolated-nitride-region non-volatile memory cell comprising:
- a semiconductor substrate;
spaced-apart source and drain regions disposed in the semiconductor substrate forming a channel therebetween;
a tunnel dielectric layer disposed over the semiconductor substrate;
a plurality of isolated regions disposed over the tunnel dielectric layer, the isolated regions formed from one of a high-temperature metal and a semiconductor material;
a plurality of isolated nitride charge-trapping regions disposed over, in contact with, and in vertical alignment with the isolated regions;
an insulating layer disposed over and between the plurality of isolated regions and isolated nitride charge-trapping regions; and
a control gate disposed above the insulating layer.
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Abstract
An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.
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Citations
8 Claims
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1. An isolated-nitride-region non-volatile memory cell comprising:
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a semiconductor substrate; spaced-apart source and drain regions disposed in the semiconductor substrate forming a channel therebetween; a tunnel dielectric layer disposed over the semiconductor substrate; a plurality of isolated regions disposed over the tunnel dielectric layer, the isolated regions formed from one of a high-temperature metal and a semiconductor material; a plurality of isolated nitride charge-trapping regions disposed over, in contact with, and in vertical alignment with the isolated regions; an insulating layer disposed over and between the plurality of isolated regions and isolated nitride charge-trapping regions; and a control gate disposed above the insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification
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Current AssigneeMicrosemi SoC Corp. (Microchip Technology Incorporated)
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Original AssigneeActel Corporation (Microchip Technology Incorporated)
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InventorsMcCollum, John
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Primary Examiner(s)Smith, Bradley K
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Assistant Examiner(s)Movva, Amar
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Application NumberUS11/152,019Time in Patent Office1,877 DaysField of Search257/314, 257/E21.681US Class Current257/314CPC Class CodesH01L 29/40117 the electrodes comprising a...H01L 29/42348 with trapping site formed b...H01L 29/66833 with a charge trapping gate...H01L 29/792 with charge trapping gate i...
