Semiconductor die packages using thin dies and metal substrates

• US 7,768,075 B2
• Filed: 04/06/2006
• Issued: 08/03/2010
• Est. Priority Date: 04/06/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Murphy, James J., Yilmaz, Hamza, Wang, Qi, Li, Minhua, Sapp, Steven, Diroll, John Robert
• Primary Examiner(s): Maldonado; Julio J
• Application Number:
  US11/400,729
• Publication Number:
  US 20070235886A1
• Time in Patent Office: 1,580 Days
• Field of Search: 257/724, 257/692, 257/730, 257/773, 257/E23.143, 257/E23.151, 257/329, 257/331, 257/332, 257/335, 257/341, 257/691, 257/728, 257/287, 257/328, 257/401, 257/723, 257/738, 257/772, 257/E27.014, 257/E27.057, 257/E29.027, 438/125, 438/459, 438/667
• US Class Current: 257/401
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

Claims

1. A semiconductor die package comprising:

a planar metal substrate within the semiconductor die package;

a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture extending through the semiconductor die, wherein the metal substrate is attached to the second surface and exposed by the at least one aperture, wherein the semiconductor die has a thickness of about 30 microns or less; and

a plurality of solder structures on the semiconductor die, wherein the plurality of solder structures includes at least one first solder structure disposed on the first surface of the semiconductor die, and at least one second solder structure disposed in the at least one aperture,

wherein the at least one second solder conductive structure is in electrical communication with the second terminal at the second surface of the semiconductor die, and the at least one second solder structure directly contacts a portion of the planar metal substrate.

2. The semiconductor die package of claim 1, wherein the package has an H-bridge configuration.

3. The semiconductor die package of claim 1, wherein the semiconductor die includes two or more apertures.

4. The semiconductor die package of claim 1, further comprising two or more conductive structures overlapping the semiconductor die.

5. The semiconductor die package of claim 1, wherein the thickness of the planar metal substrate is greater than the thickness of the semiconductor die.

6. The semiconductor die package of claim 1, wherein the semiconductor die is a first semiconductor die and wherein the semiconductor die package comprises a second semiconductor die.

7. The semiconductor die package of claim 6, wherein the second semiconductor die is attached to the planar metal substrate.

8. The semiconductor die package of claim 6 wherein the first semiconductor die comprises a first vertical power MOSFET and the second semiconductor die comprises a second vertical power MOSFET.

9. The semiconductor die package of claim 1, wherein the planar metal substrate has a thickness greater than about 50 microns.