Multi-chip package system

• US 7,768,125 B2
• Filed: 01/04/2006
• Issued: 08/03/2010
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Kuan, Heap Hoe, Chow, Seng Guan
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US11/326,211
• Publication Number:
  US 20070158809A1
• Time in Patent Office: 1,672 Days
• Field of Search: 257/E21.508, 257/E23.075, 257/777, 257/692, 257/738, 257/686, 257/685, 257/713, 257/E21.504, 257/E21.705, 257/E23.061, 257/E25.006, 257/680, 257/701, 257/705, 257/707, 257/720, 257/737, 174/260, 228/180.22, 438/613, 438/65, 438/110, 438/112
• US Class Current: 257/738
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48475 : connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01067 : Holmium [Ho]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A chip package system is provided including providing a chip having interconnects provided thereon; forming a molding compound on the chip and encapsulating the interconnects; and forming a recess in the molding compound above the interconnects to expose the interconnects.

Claims

1. A method for manufacturing a chip package system comprising:

providing a chip having interconnects provided thereon;

forming a molding compound on the chip and encapsulating the interconnects; and

forming a groove in the molding compound and the interconnects to expose the interconnects and the molding compound in a coplanar surface.

2. The method as claimed in claim 1 further comprising:

providing large interconnects on the chip that are larger than the interconnects;

forming the molding compound on the chip encapsulates the large interconnects; and

removing the molding compound above the large interconnects to expose the large interconnects.

3. The method as claimed in claim 1 further comprising:

providing a package board having wiring layers provided thereon; and

conductively connecting the interconnects to the wiring layers on the package board by the interconnects or by bond wires.

4. The method as claimed in claim 1 further comprising:

providing a package board having wiring layers provided thereon;

providing large interconnects on the chip that are larger than the interconnects;

forming the molding compound on the chip to encapsulate the large interconnects;

removing the molding compound above the large interconnects to expose the large interconnects; and

conductively connecting the interconnects to the wiring layers on the package board by the large interconnects or bond wires.

5. The method as claimed in claim 1 further comprising:

conductively connecting the interconnects on the chip to a second chip having small and large interconnects surrounded by the molding compound, the conductive connection at the small or large interconnects.

6. A method for manufacturing a chip package system comprising:

providing a wafer having interconnects provided thereon;

forming a molding compound on the wafer and encapsulating the interconnects;

forming a groove in the molding compound and the interconnects to expose the interconnects and the molding compound in a coplanar surface having evidence of being sawn; and

singulating the wafer to form first and second chip packages.

7. The method as claimed in claim 6 further comprising:

providing large interconnects on the wafer that are larger than the interconnects;

forming the molding compound on the wafer encapsulates the large interconnects;

removing the molding compound above the large interconnects to expose the large interconnects; and

the singulating the wafer forms third and fourth chip packages.

8. The method as claimed in claim 6 further comprising:

providing a package board having wiring layers provided thereon;

conductively connecting the interconnects to wiring layers on the package board by the interconnects, bond wires, or the first chip package through the second chip package.

9. The method as claimed in claim 6 further comprising:

providing a package board having wiring layers provided thereon;

providing small and large interconnects on a second wafer;

forming a second molding compound on the second wafer to encapsulate the small and large interconnects;

removing the second molding compound above the small and large interconnects to expose the small and large interconnects;

singulating the second wafer to form third and fourth chip packages; and

conductively connecting the interconnects of the first or third chip packages to the wiring layers on the package board by the interconnects, the small or large interconnects, bond wires, or through the second or fourth chip packages.

10. The method as claimed in claim 6 further comprising:

providing small and large interconnects on a second wafer;

forming a second molding compound on the second wafer to encapsulate the small and large interconnects;

removing the second molding compound above the small and large interconnects to expose the small and large interconnects;

singulating the second wafer to form third and fourth chip packages; and

conductively connecting two of the first, second, third, or fourth chip packages.

11. A chip package system comprising:

a chip having interconnects provided on the top thereof; and

a molding compound on the chip around the interconnects and having a groove in the top thereof includes the tops of the interconnects cut to be coplanar with the molding compound.

12. The system as claimed in claim 11 further comprising:

large interconnects on the chip that are larger than the interconnects; and

the molding compound on the chip around the large interconnects and exposing the tops of the large interconnects at the top of the molding compound.

13. The system as claimed in claim 11 further comprising:

a package board having wiring layers provided thereon; and

the interconnects conductively connected to the wiring layers on the package board by the interconnects or by bond wires.

14. The system as claimed in claim 11 further comprising:

a package board having wiring layers provided thereon;

large interconnects on the chip that are larger than the interconnects;

the molding compound on the chip around the large interconnects and exposing the tops of the large interconnects at the top of the molding compound; and

the interconnects and the large interconnects conductively connected to the wiring layers on the package board by the interconnects, the large interconnects, or bond wires.

15. The system as claimed in claim 11 further comprising:

the interconnects on the chip conductively connected to a second chip having small and large interconnects surrounded by the molding compound, the conductive connection at the small or large interconnects.

16. A chip package system comprising:

first and second chip packages characterized by being from the same wafer covered by a single molding compound; and

the first and second chip packages each comprises;

a chip having interconnects provided thereon, and

the molding compound on the chip around the interconnects and having a groove in the top thereof to includes the tops of the interconnects cut to be coplanar with the molding compound.

17. The system as claimed in claim 16 further comprising:

third and fourth chip packages characterized by being formed from the same wafer and covered by the single molding compound; and

the third and fourth chip packages each comprises;

a chip having large interconnects that are larger than the interconnects, and

the molding compound on the chip is around the large interconnects to expose the top of the large interconnects.

18. The system as claimed in claim 16 further comprising:

a package board having wiring layers provided thereon; and

the interconnects are conductively connected to wiring layers on the package board by the interconnects, bond wires, or the first chip package through the second chip package.

19. The system as claimed in claim 16 further comprising:

a package board having wiring layers provided thereon;

third and fourth chip packages wherein each chip package comprises;

a chip having large interconnects that are larger than the interconnects, and

a molding compound on the chip around the large interconnects and exposing the top of the large interconnects; and

the interconnects of the first or third chip packages conductively connected to the wiring layers on the package board by the interconnects, the small or large interconnects, bond wires, or through the second or fourth chip packages.

20. The system as claimed in claim 16 further comprising:

third and fourth chip packages wherein each chip package comprises;

a chip having large interconnects that are larger than the interconnects;

a molding compound on the chip around the large interconnects and exposing the top of the large interconnects; and

two of the first, second, third, or fourth chip packages are conductively connected.